DLA DSCC-VID-V62 03663 REV A-2009 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH THREE-STATE OUTPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 09-11-09 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED B

2、Y Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, LOW VOLTAGE CMOS, OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH THREE-STATE OUTPUTS, MONOLITHIC SILICON YY-MM-DD 03-10-07 APPROVED BY Thomas M

3、. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/03663 REV A PAGE 1 OF 11 AMSC N/A 5962-V009-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03663 REV A PAGE 2

4、1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance octal edge-triggered D-type flip-flop with three-state outputs microcircuit, with an operating temperature range of -40C to +105C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is

5、 the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/03663 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Ge

6、neric Circuit function 01 74LV374A-EP Octal edge-triggered D-type flip-flopwith three-state outputs 1.2.2 Case outline. The case outline are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 20 JEDEC MO-153 Plastic small-outline 1.2.3 Lead finishes. The lead finishes ar

7、e as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to +7.0 V Input voltage range (

8、VI) . -0.5 V to +7.0 V 2/ Voltage range applied to any output in the high-impedance or power-off state (VO) . -0.5 V to +7.0 V 2/ Output voltage range (VO) . -0.5 V to VCC+ 0.5 V 2/ 3/ Input clamp current (IIK) (VIVCC) 20 mA Output clamp current (IOK) (VOVCC) 50 mA Continuous output current (IO) (VO

9、= 0 to VCC) 35 mA Continuous current through VCCor GND . 70 mA Package thermal impedance (JA) . 83C/W 4/ Storage temperature range (TSTG) . -65C to +150C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and funct

10、ional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if

11、the input and output current ratings are observed. 3/ This value is limited to 5.5 V maximum. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS

12、 COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03663 REV A PAGE 3 1.4 Recommended operating conditions. 5/ 6/ Supply voltage range (VCC) . 2.0 V to 5.5 V Minimum high level input voltage (VIH): VCC= 2.0 V 1.5 V VCC= 2.3 V to 2.7 V . VCCx 0.7 VCC= 3.0 V to 3.6 V . VCCx 0.7 VCC= 4.5 V to 5.5

13、V . VCCx 0.7 Maximum low level input voltage (VIL): VCC= 2.0 V 0.5 V VCC= 2.3 V to 2.7 V . VCCx 0.3 VCC= 3.0 V to 3.6 V . VCCx 0.3 VCC= 4.5 V to 5.5 V . VCCx 0.3 Input voltage range (VI) . 0.0 V to 5.5 V Output voltage range (VO): High or low state 0.0 V to VCCThree-state 0.0 V to 5.5 V Maximum high

14、 level output current (IOH): VCC= 2.0 V -50 A VCC= 2.3 V to 2.7 V . -2 mA VCC= 3.0 V to 3.6 V . -8 mA VCC= 4.5 V to 5.5 V . -16 mA Maximum low level output current (IOL): VCC= 2.0 V 50 A VCC= 2.3 V to 2.7 V . 2 mA VCC= 3.0 V to 3.6 V . 8 mA VCC= 4.5 V to 5.5 V . 16 mA Maximum input transition rise o

15、r fall rate: VCC= 2.3 V to 2.7 V . 200 ns/V VCC= 3.0 V to 3.6 V . 100 ns/V VCC= 4.5 V to 5.5 V . 20 ns/V Operating free-air temperature range (TA) -40C to +105C 2. APPLICABLE DOCUMENTS JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices JESD 51-7 - High Effective Thermal Conduc

16、tivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 5/ Use of this product beyond the manufacturers design rules or stated parameters

17、is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 6/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking

18、 permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03663 REV A PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Ma

19、nufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating con

20、ditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.

21、2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuit. The timing waveforms

22、and test circuit shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03663 REV A PAGE 5 TABLE I. Electrical performance characteristics.

23、 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max High level output voltage VOHIOH= -50 A 2.0 V to 5.5 V 25C, -55C to 125C 01 VCC 0.1 V IOH= -2 mA 2.3 V 25C, -55C to 125C 2.0 IOH= -8 mA 3.0 V 25C, -55C to 125C 2.48 IOH= -16 mA 4.5 V 25C, -55C to 125C 3.8 Low level output v

24、oltage VOHIOL= 50 A 2.0 V to 5.5 V 25C, -55C to 125C 01 0.1 V IOL= 2 mA 2.3 V 25C, -55C to 125C 0.4 IOL= 8 mA 3.0 V 25C, -55C to 125C 0.44 IOL= 16 mA 4.5 V 25C, -55C to 125C 0.55 Input current IIVI= 5.5 V or GND 0.0 V to 5.5 V 25C, -55C to 125C 01 1.0 A 3-state output current IOZVO= VCCor GND 5.5 V

25、25C, -55C to 125C 01 5.0 A Quiescent supply current ICCVI= VCCor GND IO= 0 A 5.5 V 25C, -55C to 125C 01 20.0 A Input/output power-off leakage current IoffVIor VO= 0.0 V to 5.5 V 0.0 V 25C, -55C to 125C 01 5.0 A Input capacitance CIVI= VCCor GND 3.3 V 25C, -55C to 125C 01 2.9 TYP pF Power dissipation

26、 capacitance CpdCL= 50 pF f = 10 MHz 3.3 V 25C 01 21.1 TYP pF 5.0 V 22.8 TYP See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03663 RE

27、V A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max Quiet output, maximum dynamic VOLVOL(P)2/ CL= 50 pF 3.3 V 25C 01 0.8 V Quiet output, minimum dynamic VOLVOL(V)2/ 3.3 V 25C 01 -0.8 V Quiet output, minim

28、um dynamic VOHVOH(V)2/ 3.3 V 25C 01 2.9 TYP V High level dynamic input voltage VIH(D)2/ 3.3 V 25C 01 2.31 V Low level dynamic input voltage VIL(D)2/ 3.3 V 25C 01 0.99 V Maximum operating frequency fmax CL= 50 pF See figure 5 3.0 V and 3.6 V 25C 01 55 MHz -55C to 125C 50 4.5 V and 5.5 V 25C 85 -55C t

29、o 125C 75 Propagation delay time, CLK to Q tpdCL= 50 pF See figure 5 3.0 V and 3.6 V 25C 01 16.2 ns -55C to 125C 1.0 18.5 4.5 V and 5.5 V 25C 10.1 -55C to 125C 1.0 13.5 Propagation delay time, OE to Q tenCL= 50 pF See figure 5 3.0 V and 3.6 V 25C 01 14.5 ns -55C to 125C 1.0 17.5 4.5 V and 5.5 V 25C

30、9.6 -55C to 125C 1.0 13.0 Propagation delay time, OE to Q tdisCL= 50 pF See figure 5 3.0 V and 3.6 V 25C 01 14.0 ns -55C to 125C 1.0 16.0 4.5 V and 5.5 V 25C 8.8 -55C to 125C 1.0 10.0 See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license f

31、rom IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03663 REV A PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max Output skew tsk(o)CL= 50 pF See figure 5 3.0

32、V and 3.6 V 25C 01 1.5 ns 4.5 V and 5.5 V 25C 1.0 Pulse duration, CLK high or low twSee figure 5 3.0 V and 3.6 V 25C 01 5.0 ns -55C to 125C 5.5 4.5 V and 5.5 V 25C 5.0 -55C to 125C 5.0 Setup time, data before CLK twSee figure 5 3.0 V and 3.6 V 25C 01 4.5 ns -55C to 125C 4.5 4.5 V and 5.5 V 25C 3.0 -

33、55C to 125C 3.0 Hold time, data after CLK twSee figure 5 3.0 V and 3.6 V 25C 01 2.0 ns -55C to 125C 2.0 4.5 V and 5.5 V 25C 2.0 -55C to 125C 2.0 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range.

34、 Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Characteristics are for surface-mount packages only. Provided

35、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03663 REV A PAGE 8 Case X Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A

36、- 1.20 - .047 E 4.30 4.50 .169 .177 A1 0.05 0.15 .002 .006 E1 6.20 6.60 .244 .260 b 0.19 0.30 .007 .012 e 0.65 NOM .026 NOM c 0.15 NOM .006 NOM L 0.50 0.75 .020 .030 D 6.40 6.60 .252 .260 NOTES: 1. This drawing is subject to change without notice. 2. Body dimensions do not include mold flash or prot

37、rusion not to exceed 0.15 mm. 3. Falls within JEDEC MO-153. 4. All linear dimensions are shown in millimeters (inches). Inches equivalents are given for general information only. FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-

38、,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03663 REV A PAGE 9 (each flip-flop) Inputs Output Q OE CLK D L L L H L X H L X X H L Q0Z X = Immaterial Z = High impedance state = Rising edge of CLK. FIGURE 2. Truth table. FIGURE 3. Logic diagram. Device type

39、01 Case outlines: X and Y Terminal number Terminal symbol Terminal number Terminal symbol 1 11 CLK 2 1Q 12 5Q 3 1D 13 5D 4 2D 14 6D 5 2Q 15 6Q 6 3Q 16 7Q 7 3D 17 7D 8 4D 18 8D 9 4Q 19 8Q 10 GND 20 VCCFIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted

40、 without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03663 REV A PAGE 10 Notes: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the out

41、put control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO= 50, tr 3 ns, tf 3 ns. 4. The outputs are measured one at a ti

42、me with one input transition per measurement. 5. tPLZand tPHZare the same as tdis. 6. tPZLand tPZHare the same as ten. 7. tPHLand tPLHare the same as tpd. 8. For 3-state and Open Drain outputs tests: tPLH/tPHLS1 = Open tPLZ/tPZLS1 = VCCtPHZ/tPZHS1 = GND Open Drain S1 = VCCFIGURE 5. Timing waveforms

43、and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03663 REV A PAGE 11 4. QUALITY ASSURANCE PROVISIONS 4.1 Product assurance requirements. The manuf

44、acturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARA

45、TION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class

46、 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of

47、 supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top-Side Marking V62/03663-01XE 01295 SN74LV374ATPWREP LV374AEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest lane P