DLA DSCC-VID-V62 03670 REV C-2012 MICROCIRCUIT DIGITAL CMOS THREE-PORT CABLE TRANSCEIVER ARBITER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add device type -02 as a substitute for device type -01. Obsolete device type -01. Correct vendor datasheet errors for limits of VDD, VOD, and IOZparameters. Update boilerplate to current revision. - CFS 04-11-09 Thomas M. Hess B Add device type 03. - PHN 0

2、6-07-12 Thomas M. Hess C Update boilerplate paragraphs to current requirements. - PHN 12-07-23 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE RE

3、V STATUS OF PAGES REV C C C C C C C C C C C C C C C C PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, CMOS, THREE-PORT CABLE

4、 TRANSCEIVER/ARBITER, MONOLITHIC SILICON 03-08-19 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/03670 REV C PAGE 1 OF 16 AMSC N/A 5962-V083-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUM

5、BUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03670 REV C PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance Three-Port Cable Transceiver/Arbiter microcircuit, with an operating temperature range of -40C to +110C. 1.2 Vendor Item Drawing Administrati

6、ve Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/03670 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See

7、1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 1/ TSB41BA3-EP Three-Port Cable Transceiver/Arbiter 02 1/ TSB41BA3A-EP Three-Port Cable Transceiver/Arbiter 03 TSB41BA3B-EP Three-Port Cable Transceiver/Arbiter 1.2.2 Case outline(s). The case outline(s) are as specified herein. Ou

8、tline letter Number of pins JEDEC PUB 95 Package style X 80 JEDEC MS-026 Plastic Quad Flatpack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Pall

9、adium E Gold flash palladium 1/ Device type -02 is a substitute for the obsolete device type -01. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03670 REV C PAGE

10、3 1.3 Absolute maximum ratings. 2/ Supply voltage range (VDD) . -0.3 V to +4.0 V 3/ Input voltage range (VI) . -0.5 V to VDD+ 0.5 V 3/ Output voltage range at any output (VO) . -0.5 V to VDD+ 0.5 V Continuous total power dissipation: . See dissipation rating table Operating free-air temperature rang

11、e (TA) -40C to +110C Storage temperature range (TSTG) . -65C to +150C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260C Dissipation rating table: Case Outline TA 65C Power Rating Derating Factor 4/ Above TA= 25C TA= 70C Power rating TA= 110C Power rating Case X 5/ 5.05 W 52.5 mW/C 2.

12、69 W 587 mW Case X 6/ 3.05 W 31.7 mW/C 1.62 W 355 mW Case X 7/ 2.01 W 20.3 mW/C 1.1 W 284 mW 1.4 Recommended operating conditions. 8/ Supply voltage range (3.3 VDD): Source power node . +3.0 V to +3.6 V Non-source power node +3.0 V to +3.6 V 9/ Supply voltage range (1.8 VDD) . +1.75 V to +2.0 V Mini

13、mum high level input voltage (VIH): LREQ, CTL0, CTL1, D0-D7, LCLK_PMC +2.6 V Device 01: S5_LKON_DS2, S4_DS1, S3_DS0, S2_PC0, S1_PC1, S0_PC2, SLPEN, PD, BMODE,TPBIAS0_SD0, TPBIAS1_SD1, TPBIAS2_SD2 0.7xVDDDevice 02, 03: S5_LKON, S4, S3, S2_PC0, S1_PC1, S0_PC2, SLPEN, PD, BMODE, TPBIAS0_SD0, TPBIAS1_SD

14、1, TPBIAS2_SD2 0.7xVDDRESETz or RESET 0.6xVDD 10/ Maximum low level input voltage (VIL): LREQ, CTL0, CTL1, D0-D7, LCLK_PMC +1.2 V Device 01: S5_LKON_DS2, S4_DS1, S3_DS0, S2_PC0, S1_PC1, S0_PC2, SLPEN, PD, BMODE, TPBIAS0_SD0, TPBIAS1_SD1, TPBIAS2_SD2 0.2xVDDDevice 02, 03: S5_LKON, S4, S3, S2_PC0, S1_

15、PC1, S0_PC2, SLPEN, PD, BMODE, TPBIAS0_SD0, TPBIAS1_SD1, TPBIAS2_SD2 . 0.2xVDDRESETz or RESET 0.3xVDD10/ _ 2/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any o

16、ther conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3/ All voltage values, except differential I/O bus voltages, are with respect to network ground. 4/ This i

17、s the inverse of the traditional junction to ambient thermal resistance (RJA). 5/ 2 oz. trace and copper pad with solder. 6/ 2 oz. trace and copper pad without solder. 7/ For more information see manufacturer application report. 8/ Use of this product beyond the manufacturers design rules or stated

18、parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 9/ For a node that does not source power; see Section 4.2.2.2 in IEEE 1394a-2000. 10/ RESETz is for device type 01 and 02; RESET is for device

19、type 03 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03670 REV C PAGE 4 1.4 Recommended operating conditions - Continued. Output current (IOL/OH): Device 01: CT

20、L0, CTL1, D0-D7, S5_LKON_DS2, PINT, PCLK -4.0 mA to +4.0 mA Device 02, 03: CTL0, CTL1, D0-D7, S5_LKON, PINT, PCLK . -4.0 mA to +4.0 mA Output current (IO) (TPBIAS outputs) -5.6 mA to +1.3 mA Operating free-air temperature range (TA) -40C to +110C Maximum junction temperature (TJ): RJA= 19C/W (TA= 11

21、0C) +124.13C 1394b Differential input voltage (VID): Cable inputs, during data reception . 200 mV to 800 mV 1394a Differential input voltage range (VID): Cable inputs, during data reception . 118 mV to 260 mV Cable inputs, during arbitration 168 mV to 265 mV 1394a Common-mode input voltage (VIC): TP

22、B cable inputs, source power node . 0.4706 V to 2.515 V TPB cable inputs, non-source power node 0.4706 V to 2.015 V 9/ Minimum power-up reset time (t(pu) (RESETz or RESET input) 2 ms 10/ 11/ Maximum receive input jitter: TPA, TPB cable inputs, S100 operation 1.08 ns TPA, TPB cable inputs, S200 opera

23、tion 0.5 ns TPA, TPB cable inputs, S400 operation 0.315 ns Maximum receive input skew: Between TPA and TPB cable inputs, S100 operation . 0.8 ns Between TPA and TPB cable inputs, S200 operation . 0.55 ns Between TPA and TPB cable inputs, S400 operation . 0.5 ns 2. APPLICABLE DOCUMENTS JEDEC SOLID ST

24、ATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) THE INSTITUTE OF ELEC

25、TRICAL AND ELECTRONICS ENGINEERS (IEEE) IEEE 1394-1995 - (1394) Standard for High-Performance Serial Bus IEEE 1394a-2000 - (1394) Standard for High-Performance Serial Bus Supplement IEEE 1394b-2002 - (1394) Standard for High-Performance Serial Bus Supplement (Copies of these documents are available

26、online at http:/www.ieee.org or from the IEEE Service Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 088551331. 11/ Time after valid clock received at PHY XI input terminal. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER,

27、 COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03670 REV C PAGE 5 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ES

28、DS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as spec

29、ified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Block diagrams. The block diagrams sha

30、ll be as shown in figure 2. 3.5.3 Terminal connections. The terminal connections shall be as shown in figure 3. 3.5.4 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as shown in figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without l

31、icense from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03670 REV C PAGE 6 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test conditions unless otherwise specified VDDTemperature, TADevice type Limits Unit Min Max DEVICE Supply cur

32、rent 3.3 VDDIDD2/ 3.3 V 25C All 75 Typ mA Power status threshold, CPS input V(TH)3/ 400 k resistor 3.0 V and 3.6 V -40C to +110C 4.7 7.5 V High level output voltage VOHIOH= -4 mA For CTL0, CTL1, D0-D7, PCLK, S5_LKON_DS2 or S5_LKON outputs. 3.0 V and 3.6 V 2.8 V Low level output voltage VOLIOL= 4 mA

33、For CTL0, CTL1, D0-D7, PCLK, S5_LKON_DS2 or S5_LKON outputs. 3.0 V and 3.6 V 0.4 V Positive peak bus holder current IBH+VI= 0 V to VDDFor CTL0, CTL1, D0-D7, LREQ. 3.6 V 0.05 1.0 mA Negative peak bus holder current IBH-VI= 0 V to VDDFor CTL0, CTL1, D0-D7, LREQ. 3.6 V -1.0 -0.05 mA Off-state output cu

34、rrent IOZVO= VDDor 0 V For CTL0, CTL1, D0-D7, S5_LKON_DS2 or S5_LKON I/Os 3.0 V and 3.6 V 30 A Pullup current, RESETz or RESET input 4/ IIRSTVI= 1.5 V or 0 V 3.0 V and 3.6 V -90 -20 A Output voltage, TPBIAS VOAt rated IOcurrent. 3.0 V and 3.6 V 1.665 2.015 V See footnotes at end of table. Provided b

35、y IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03670 REV C PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions unless otherwi

36、se specified VDDTemperature, TADevice type Limits Unit Min Max DRIVER 1394a differential output voltage VODRL= 56 See figure 4. 3.0 V and 3.6 V -40C to +110C All 172 265 mV 1394b differential output voltage VOD300 800 mV Driver difference current IDIFFDrivers enabled, speed signaling off For TPA+, T

37、PA-, TPB+, TPB-. -1.05 5/ 1.05 5/ mA Common-mode speed signaling current ISP200S200 speed signaling enabled For TPB+, TPB-. -4.84 6/ -2.53 6/ mA ISP400S400 speed signaling enabled For TPB+, TPB-. -12.4 6/ -8.10 6/ mA Off state differential voltage VOFFDrivers disabled. See figure 4. 20 mV RECEIVER D

38、ifferential impedance zidDrivers disabled. 3.0 V and 3.6 V -40C to +110C All 4 k 4 pF Common-mode impedance zicDrivers disabled. 20 k 24 pF Receiver input threshold voltage VTH-RDrivers disabled. -30 30 mV Cable bias detect threshold voltage VTH-CBDrivers disabled. For TPB+ and TPB- cable inputs 0.6

39、 1.0 V Positive arbitration comparator threshold voltage VTH+Drivers disabled. 89 168 mV Negative arbitration comparator threshold voltage VTH-Drivers disabled. -168 -89 mV Speed signal threshold VTH-SP200TPBIAS-TPA common- mode voltage, drivers disabled. 49 131 mV VTH-SP400314 396 mV See footnotes

40、at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03670 REV C PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Tes

41、t conditions unless otherwise specified VDDTemperature, TA Device type Limits Unit Min Max Thermal Characteristics Junction-to-ambient thermal resistance RJA7/ 3.3 V +25C All 19.04 Typ C/W Junction-to-case thermal resistance RJC0.17 Typ C/W Junction-to-ambient thermal resistance RJA8/ 31.52 Typ C/W

42、Junction-to-case thermal resistance RJC0.17 Typ C/W Junction-to-ambient thermal resistance RJA9/ 49.17 Typ C/W Junction-to-case thermal resistance RJC3.11 Typ C/W Switching Characteristics TP differential rise time, transmit tr10% to 90% At 1394 connector. 3.0 V and 3.6 V -40C to +110C All 0.3 0.8 n

43、s TP differential fall time, transmit tf90% to 10% At 1394 connector. 0.3 0.8 ns Setup time, CTL0, CTL1, D1-D7, LREQ to PCLK tsu1394a-2000 50% to 50% See figure 4. 2.5 ns Hold time, CTL0, CTL1, D1-D7, LREQ after PCLK th1394a-2000 50% to 50% See figure 4. 0 ns Setup time, CTL0, CTL1, D1-D7, LREQ to L

44、CLK_PMC tsu1394b 50% to 50% See figure 4. 2.5 ns Hold time, CTL0, CTL1, D1-D7, LREQ after LCLK_PMC th1394b 50% to 50% See figure 4. 0 ns Delay time, PCLK to CTL0, CTL1, D1-D7, PINT td1394a-2000 and 1394b 50% to 50% See figure 4. 0.5 7.0 ns See footnotes at end of table. Provided by IHSNot for Resale

45、No reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03670 REV C PAGE 9 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions unless otherwise specified VDDTem

46、perature, TADevice type Limits Unit Min Max LPS Timing Parameters LPS low time TLPSLWhen pulsed. 10/ 3.0 V and 3.6 V -40C to +110C 01, 02 0.09 2.60 s LPS high time TLPSHWhen pulsed. 10/ 0.021 2.60 s LPS duty cycle When pulsed. 11/ 20% 60% LPS reset time TLPS_RESETTime for PHY to recognize LPS deasse

47、rted and reset the interface. 2.60 2.68 s LPS disable time, TLPS_DISABLETime for PHY to recognize LPS deasserted and disable the interface. 26.03 26.11 s Restore time TRESTORETime to permit optional isolation circuits to restore during an interface reset. 15 23 11/ s PCLK activation time TCLK_ACTIVA

48、TETime for PCLK to be activated from reassertion of LPS. PHY not in low-power state. 60 ns Time for PCLK to be activated from reassertion of LPS. PHY in low-power state. 5.3 7.3 ms See footnotes on next sheet. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTE