DLA DSCC-VID-V62 04606 REV B-2012 MICROCIRCUIT DIGITAL FIXED POINT DIGITAL SIGNAL PROCESSOR MONOLITHIC SILICON.pdf

1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Correct lead finish. Update boilerplate. - CFS 05-11-08 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 12-03-22 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43

2、218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV B B B PAGE 40 41 42 REV B B B B B B B B B B B B B B B B B B B B B B PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 REV STATUS OF PAGES REV B B B B B B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 1

3、2 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, FIXED POINT DIGITAL SIGNAL PROCESSOR, MONOLITHIC SILICON 04-01-28 APPROVED BY Thomas M. Hess SIZE A CO

4、DE IDENT. NO. 16236 DWG NO. V62/04606 REV B PAGE 1 OF 42 AMSC N/A 5962-V044-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04606 REV B PAGE 2 1. SCOPE 1.1 Scop

5、e. This drawing documents the general requirements of a fixed point digital signal processor, with an operating temperature range of -40C to +105C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an admin

6、istrative control number for identifying the item on the engineering documentation: V62/04606 01 X A Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device Generic number Circuit function 01 SM320C6201-EP Fixed point digital signal pro

7、cessor 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 352 JEDEC MO-151/BAR-2 Plastic ball grid array 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufactur

8、er: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other 1.3 Absolute maximum ratings. 2/ Supply voltage range, (CVDD) . -0.3 V to +2.3 V 3/ Supply voltage range, (DVDD) . -0.3 V to +4.0 V 3/ Input voltage range . -0.3 V to +4.0 V Output v

9、oltage range -0.3 V to +4.0 V Operating case temperature ranges, (TC): (A version) . -40C to +105C Storage temperature range, (TSTG) -65C to +150C 1/ Users are cautioned to review the manufacturers data manual for additional user information relating to this device. 2/ Stresses beyond those listed u

10、nder “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated condition

11、s for extended periods may affect device reliability. 3/ All voltage values are with respect to VSS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04606 REV B PA

12、GE 3 1.4 Recommended operating conditions. Supply voltage, (CVDD) . +1.71 V to +1.89 V Supply voltage, (DVDD) . +3.14 V to +3.46 V Supply ground (VSS) . 0.0 V High level input voltage, (VIH) . +2.0 V minimum Low level input voltage, (VIL) +0.8 V maximum High level output current, (IOH) . -12 mA maxi

13、mum Low level output current, (IOL) +12 mA maximum Operating case temperature (TC) (A version) . -40C to +105C 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at

14、http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name,

15、CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electr

16、ical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figu

17、re 1. 3.5.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.5.3 Block diagram. The block diagram shall be as specified on figure 3. 3.5.4 Load circuit. The load circuit shall be as specified on figure 4. 3.5.5 Timing waveforms. The timing waveforms shall be as spe

18、cified on figure 5-31. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04606 REV B PAGE 4 TABLE I. Electrical performance characteristics. 1/ No. Test Symbol Test

19、condition -40C TC+105C 1.71 V CVDD 1.89 V 3.14 V DVDD 3.46 V unless otherwise noted Limits Unit Min Max High level output voltage VOHDVDD= MIN, IOH= MAX 2.4 V Low level output voltage VOLDVDD= MIN, IOL= MAX 0.6 V Input current 2/ IIVI= VSSto DVDD10 A Off state output current IOZVO= DVDDor 0 V 10 A S

20、upply current, CPU + CPU memory access 3/ IDD2VCVDD= NOM, CPU clock = 167 MHz 380 Typ mA Supply current, peripheral 3/ IDD2VCVDD= NOM, CPU clock = 167 MHz 240 Typ mA Supply current, I/O pins 3/ IDD3VDVDD= NOM, CPU clock = 167 MHz 90 Typ mA Input capacitance CI10 pF Output capacitance CO10 pF No. Tes

21、t Symbol Test condition -40C TC+105C 1.71 V CVDD 1.89 V 3.14 V DVDD 3.46 V unless otherwise noted Limits Units CLKMODE = x4 CLKMODE = x1 Min Max Min Max INPUT AND OUTPUT CLOCKS Timing requirements for CLKIN 4/ 5/ 1 Cycle time, CLKIN tc(CLKIN)See figure 7 20 5 ns 2 Pulse duration, CLKIN high tw(CLKIN

22、H)0.4C 0.45C 3 Pulse duration, CLKIN low tw(CLKINL)0.4C 0.45C 4 Transition time, CLKIN tt(CLKIN)5 0.6Switching characteristics over recommended operating conditions for CLKOUT1 4/ 6/ 7/ 1 Cycle time, CLKOUT1 tc(CKO1)See figure 8 P-0.7 P+0.7 P-0.7 P+0.7 ns 2 Pulse duration, CLKOUT1 high tw(CKO1H)(P/2

23、)-0.5 (P/2)+0.5 PH-0.5 PH+0.5 3 Pulse duration, CLKOUT1 low tw(CKO1L)(P/2)-0.5 (P/2)+0.5 PL-0.5 PL+0.5 4 Transition time, CLKOUT1 tt(CKO1)0.6 0.6 See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMB

24、US COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04606 REV B PAGE 5 TABLE I. Electrical performance characteristics - Continued. 1/ No. Test Symbol Test condition -40C TC+105C 1.71 V CVDD 1.89 V 3.14 V DVDD 3.46 V unless otherwise noted Limits Unit Min Max INPUT AND OUTPUT CLOCKS (CONTINUED

25、) Switching characteristic over recommended operating conditions for CLKOUT2 4/ 6/ 1 Cycle time, CLKOUT tc(CKO2)See figure 9 2P0.7 2P+0.7 ns 2 Pulse duration, CLKOUT2 high tw(CKO2H)P0.7 P+0.7 3 Pulse duration, CLKOUT2 low tw(CKO2L)P0.7 P+0.7 4 Transition time, CLKOUT2 tt(CKO2)0.6Switching characteri

26、stics over recommended operating conditions for the relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1 6/ 1 Delay time, CLKOUT1 edge to SSCLK edge td(CKO1-SSCLK)See figure 10 (P/2)+0.2 (P/2)+4.2 ns 2 Delay time, CLKOUT1 edge to SSCLH edge (1/2 clock rate) td(CKO1-SSCLK1/2)(P/2)-1 (P/2)+2.4 3 Delay tim

27、e, CLKOUT1 edge to CLKOUT2 edge td(CKO1-CKO2)(P/2)-1 (P/2)+2.4 4 Delay time, CLKOUT1 edge to SDCLK edge td(CKO1-SDCLK)(P/2)-1 (P/2)+2.4 ASYNCHRONOUS MEMORY TIMING Timing requirements for asynchronous memory cycles 8/ 6 Setup time, read EDx valid before CLKOUT1 high tsu(EDV-CKO1H)See figure 11 4 ns 7

28、 Hold time, read EDx valid after CLKOUT1 high th(CKO1H-EDV)0.8 10 Setup time, ARDY valid before CLKOUT1 high tsu(ARDY-CKO1H)3 11 Hold time, read ARDY valid after CLKOUT1 high th(CKO1H-ARDY)1.8 Switching characteristics over recommended operating conditions for asynchronous memory cycles 9/ 1 Delay t

29、ime, CLKOUT1 high to CEx valid td(CKO1H-CEV)See figure 11 -0.2 4 ns 2 Delay time, CLKOUT1 high to BEx valid td(CKO1H-BEV)3 Delay time, CLKOUT1 high to BEx invalid td(CKO1H-BEIV)-0.2 4 Delay time, CLKOUT1 high to EAx valid td(CKO1H-EAV)4 5 Delay time, CLKOUT1 high to EAx invalid td(CKO1H-EAIV)-0.2 8

30、Delay time, CLKOUT1 high to AOE valid td(CKO1H-AOEV)4 9 Delay time, CLKOUT1 high to ARE valid td(CKO1H-AREV)-0.2 12 Delay time, CLKOUT1 high to EDx valid td(CKO1H-EDV)4 13 Delay time, CLKOUT1 high to EDx invalid td(CKO1H-EDIV)-0.2 14 Delay time, CLKOUT1 high to AWE valid td(CKO1H-AWEV)4 See notes at

31、 end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04606 REV B PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ No. Test Symbol T

32、est condition -40C TC+105C 1.71 V CVDD 1.89 V 3.14 V DVDD 3.46 V unless otherwise noted Limits Unit Min Max SYNCHRONOUS BURST MEMORY TIMING Timing requirements for synchronous burst SRAM cycles (full rate SSCLK) 7 Setup time, read EDx valid before SSCLK high tsu(EDV-SSCLKH)See figure 12 1.5 ns 8 Hol

33、d time, read EDx valid after SSCLK high th(SSCLKH-EDV)1.5Switching characteristics over recommended operating conditions for synchronous burst SRAM cycles (full rate SSCLK) 10/ 1 Output setup time, CEx valid before SSCLK high tosu(CEV-SSCLKH)See figure 12 0.5P-1.3 ns 2 Output hold time, CEx valid af

34、ter SSCLK high toh(SSCLKH-CEV)0.5P-2.33 Output setup time, BEx valid before SSCLK high tosu(BEV-SSCLKH)0.5P-1.34 Output hold time, BEx invalid after SSCLK high toh(SSCLKH-BEIV)0.5P-2.3 5 Output setup time, EAx valid before SSCLK high tosu(EAV-SSCLKH)0.5P-1.36 Output hold time, EAx invalid after SSCL

35、K high toh(SSCLKH-EAIV)0.5P-2.39 Output setup time, SSADS valid before SSCLK high tosu(ADSV-SSCLKH)0.5P-1.3 10 Output hold time, SSADS valid after SSCLK high toh(SSCLKH-ADSV)0.5P-2.311 Output setup time, SSOE valid before SSCLK high tosu(OEV-SSCLKH)0.5P-1.312 Output hold time, SSOE valid after SSCLK

36、 high toh(SSCLKH-OEV)0.5P-2.3 13 Output setup time, EDx valid before SSCLK high tosu(EDV-SSCLKH)0.5P-1.314 Output hold time, EDx invalid after SSCLK high toh(SSCLKH-EDIV)0.5P-2.315 Output setup time, SSWE valid before SSCLK high tosu(WEV-SSCLKH)0.5P-1.3 16 Output hold time, SSWE valid after SSCLK hi

37、gh toh(SSCLKH-WEV)0.5P-2.3See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04606 REV B PAGE 7 TABLE I. Electrical performance characteris

38、tics - Continued. 1/ No. Test Symbol Test condition -40C TC+105C 1.71 V CVDD 1.89 V 3.14 V DVDD 3.46 V unless otherwise noted Limits Unit Min Max SYNCHRONOUS BURST MEMORY TIMING (CONTINUED) Timing requirements for synchronous burst SRAM cycles (half rate SSCLK) 7 Setup time, read EDx valid before SS

39、CLK high tsu(EDV-SSCLKH)See figure 13 2.5 ns 8 Hold time, read EDx valid after SSCLK high th(SSCLKH-EDV)1.5Switching characteristics over recommended operating conditions for synchronous burst SRAM cycles (half rate SSCLK) 11/ 1 Output setup time, CEx valid before SSCLK high tosu(CEV-SSCLKH)See figu

40、re 13 1.5P-3 ns 2 Output hold time, CEx valid after SSCLK high toh(SSCLKH-CEV)0.5P-1.53 Output setup time, BEx valid before SSCLK high tosu(BEV-SSCLKH)1.5P-34 Output hold time, BEx invalid after SSCLK high toh(SSCLKH-BEIV)0.5P-1.5 5 Output setup time, EAx valid before SSCLK high tosu(EAV-SSCLKH)1.5P

41、-36 Output hold time, EAx invalid after SSCLK high toh(SSCLKH-EAIV)0.5P-1.59 Output setup time, SSADS valid before SSCLK high tosu(ADSV-SSCLKH)1.5P-3 10 Output hold time, SSADS valid after SSCLK high toh(SSCLKH-ADSV)0.5P-1.511 Output setup time, SSOE valid before SSCLK high tosu(OEV-SSCLKH)1.5P-312

42、Output hold time, SSOE valid after SSCLK high toh(SSCLKH-OEV)0.5P-1.5 13 Output setup time, EDx valid before SSCLK high tosu(EDV-SSCLKH)1.5P-314 Output hold time, EDx invalid after SSCLK high toh(SSCLKH-EDIV)0.5P-1.515 Output setup time, SSWE valid before SSCLK high tosu(WEV-SSCLKH)1.5P-3 16 Output

43、hold time, SSWE valid after SSCLK high toh(SSCLKH-WEV)0.5P-1.5See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04606 REV B PAGE 8 TABLE I

44、. Electrical performance characteristics - Continued. 1/ No. Test Symbol Test condition -40C TC+105C 1.71 V CVDD 1.89 V 3.14 V DVDD 3.46 V unless otherwise noted Limits Unit Min Max SYNCHRONOUS DRAM TIMING Timing requirements for synchronous DRAM cycles 7 Setup time, read EDx valid before SDCLK high

45、 tsu(EDV-SDCLKH)See figure 14 0.5 ns 8 Hold time, read EDx valid after SDCLK high th(SDCLKH-EDV)3 Switching characteristics over recommended operating conditions for synchronous DRAM cycles 11/ 1 Output setup time, CEx valid before SDCLK high tosu(CEV-SDCLKH)See figure 14-16 1.5P-3.5 ns 2 Output hol

46、d time, CEx valid after SDCLK high toh(SDCLKH-CEV)0.5P-13 Output setup time, BEx valid before SDCLK high tosu(BEV-SDCLKH)1.5P-3.54 Output hold time, BEx invalid after SDCLK high toh(SDCLKH-BEIV)0.5P-1 5 Output setup time, EAx valid before SDCLK high tosu(EAV-SDCLKH)1.5P-3.56 Output hold time, EAx in

47、valid after SDCLK high toh(SDCLKH-EAIV)0.5P-19 Output setup time, SDCAS valid before SDCLK high tosu(SDCAS-SDCLKH)1.5P-3.5 10 Output hold time, SDCAS valid after SDCLK high toh(SDCLKH-SDCAS)0.5P-111 Output setup time, EDx valid before SDCLK high tosu(EDV-SDCLKH)1.5P-3.512 Output hold time, EDx inval

48、id after SDCLK high toh(SDCLKH-EDIV)0.5P-1 13 Output setup time, SDWE valid before SDCLK high tosu(SDWE-SDCLKH)1.5P-3.514 Output hold time, SDWE valid after SDCLK high toh(SDCLKH-SDWE)0.5P-115 Output setup time, SDA10 valid before SDCLK high tosu(SDA10V-SDCLKH)1.5P-3.5 16 Output hold time, SDA10 valid after SDCLK high toh(SDCLKH-SDA10IV)0.5P-117 Output setup time, SDRAS valid before SDCLK high tosu(SDRAS-SDCLKH)1.5P-3.518 Output hold time, SDRAS valid after SDCLK high toh(SDCLKH-SDRAS)0.5P-1 See n