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本文(DLA DSCC-VID-V62 04614 REV A-2010 MICROCIRCUIT DIGITAL ADVANCED CMOS HEX INVERTER MONOLITHIC SILICON.pdf)为本站会员(花仙子)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA DSCC-VID-V62 04614 REV A-2010 MICROCIRCUIT DIGITAL ADVANCED CMOS HEX INVERTER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YY-MM-DD) APPROVED A Update boilerplate paragraphs to current requirements. - PHN 10-01-19 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 PMIC N/A PREPARED

2、BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED CMOS, HEX INVERTER, MONOLITHIC SILICON YY-MM-DD 03-11-13 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/0461

3、4 REV A PAGE 1 OF 9 AMSC N/A 5962-V025-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04614 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the genera

4、l requirements of a high performance hex inverter microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for i

5、dentifying the item on the engineering documentation: V62/04614 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 74AC04-EP Hex inverter 1.2.2 Case outline(s). The case outlines are as specif

6、ied herein. Outline letter Number of pins JEDEC PUB 95 Package style X 14 MS-012 Plastic small-outline package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C Go

7、ld plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04614 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply volt

8、age range (VCC) . -0.5 V to 7.0 V Input voltage range (VI) . -0.5 V to VCC+ 0.5 V 2/ Output voltage range (VO) . -0.5 V to VCC+ 0.5 V 2/ Input clamp current (IIK) (VIVCC) . 20 mA Output clamp current (IOK) (VOVCC) . 20 mA Continuous output current (IO) (VO= 0 to VCC) 50 mA Continuous current through

9、 VCCor GND . 200 mA Package thermal impedance (JA) . 86C/W 3/ Storage temperature range (TSTG) . -65C to 150C 4/ 1.4 Recommended operating conditions. 5/ 6/ Supply voltage range (VCC) . 2.0 V to 6.0 V Input voltage range (VI) . 0.0 V to VCCOutput voltage range (VO) . 0.0 V to VCCMinimum high level i

10、nput voltage (VIH): VCC= 3.0 V 2.1 V VCC= 4.5 V 3.15 V VCC= 5.5 V 3.85 V Maximum low level input voltage (VIL): VCC= 3.0 V 0.9 V VCC= 4.5 V 1.35 V VCC= 5.5 V 1.65 V Maximum high level output current (IOH): VCC= 3.0 V -12 mA VCC= 4.5 V -24 mA VCC= 5.5 V -24 mA Maximum low level output current (IOL):

11、VCC= 3.0 V 12 mA VCC= 4.5 V 24 mA VCC= 5.5 V 24 mA Maximum input transition rise or fall rate (t/v) . 8 ns/V Operating free-air temperature range (TA) -55C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only

12、, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output voltage ratings may be e

13、xceeded if the input and output current ratings are observed. 3/ The package thermal impedance is calculated in accordance with JESD 51-7. 4/ Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. 5/ Use of

14、 this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 6/ All unused inputs of the device must be held at VCCor GND to ensure proper dev

15、ice operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04614 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 - Registered and Standard Outlines for Semic

16、onductor Devices JEDEC STD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industry Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking.

17、 Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part

18、number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, constructio

19、n, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal conne

20、ctions. The terminal connections shall be as shown in figure 4. 3.5.5 Test circuit and timing waveforms. The test circuit and timing waveforms shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUM

21、BUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04614 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max High level output voltage VOHIOH= -50 A 3.0 V 25C, -55C to 125C All 2.9 V 4.5 V 4.4 5.5 V 5.4 IOH

22、= -12 mA 3.0 V 25C 2.56 -55C to 125C 2.4 IOH= -24 mA 4.5 V 25C 3.86 -55C to 125C 3.7 5.5 V 25C 4.86 -55C to 125C 4.7 Low level output voltage VOLIOL= 50 A 3.0 V 25C, -55C to 125C All 0.1 V 4.5 V 0.1 5.5 V 0.1 IOL= 12 mA 3.0 V 25C 0.36 -55C to 125C 0.5 IOL= 24 mA 4.5 V 25C 0.36 -55C to 125C 0.5 5.5 V

23、 25C 0.36 -55C to 125C 0.5 Input current IIVI= VCCor GND 5.5 V 25C All 0.1 A -55C to 125C 1.0 Quiescent supply current ICCVI= VCCor GND IO= 0 A 5.5 V 25C All 2.0 A -55C to 125C 40.0 Input capacitance CIVI= VCCor GND 25C All 2.8 TYP pF Power dissipation capacitance CPDCL= 50 pF f = 1 MHz 5.0 V 25C Al

24、l 45 TYP pF Propagation delay time, A to Y tPLHSee figure 5 3.0 V and 3.6 V 25C All 1.5 9.0 ns -55C to 125C 1.0 11.0 4.5 V and 5.5 V 25C 1.5 7.0 -55C to 125C 1.0 8.5 tPHLSee figure 5 3.0 V and 3.6 V 25C All 1.5 8.5 ns -55C to 125C 1.0 10.0 4.5 V and 5.5 V 25C 1.5 6.5 -55C to 125C 1.0 7.5 1/ Testing

25、and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parame

26、tric testing, product performance is assured by characterization and/or design. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04614 REV A PAGE 6 Case X Dimension

27、s Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max A .069 1.75 E .150 .157 3.81 4.00 A1 .004 .010 0.10 0.25 E1 .228 .244 5.80 6.20 b .014 .020 0.35 0.51 e .050 BSC 1.27 BSC c .008 NOM 0.20 NOM L .016 .044 0.40 1.12 D .337 .344 8.55 8.75 NOTES: 1. All linear dimensi

28、ons are in inches (millimeters). 2. This case outline is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 inches (0.15 mm). 4. Fall within JEDEC MS-012. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking

29、 permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04614 REV A PAGE 7 (each inverter) Input A Output Y H L L H H = High voltage level L = Low voltage level FIGURE 2. Truth table. FIGURE 3. Logic diagram. Device type 01 Case

30、outlines: X Terminal number Terminal symbol Terminal number Terminal symbol 1 1A 8 4Y 2 1Y 9 4A 3 2A 10 5Y 4 2Y 11 5A 5 3A 12 6Y 6 3Y 13 6A 7 GND 14 VCCFIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CEN

31、TER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04614 REV A PAGE 8 NOTES: 1. CLincludes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO= 50 , tr 2.5 ns, tf 2.5 ns. 3. the outputs are measured one at a

32、time with one input transition per measurement. 4. For tPLH/tPHLtests, S1 = Open FIGURE 5. Test circuit and timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 D

33、WG NO. V62/04614 REV A PAGE 9 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, class

34、ification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOT

35、ES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes withou

36、t notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administra

37、tive control number 1/ Device manufacturer CAGE code Vendor part number Top side marking V62/04614-01XE 01295 SN74AC04MDREP SAC04MEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-

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