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本文(DLA DSCC-VID-V62 04618 REV A-2010 MICROCIRCUIT DIGITAL-LINEAR LOW VOLTAGE 10-BIT ANALOG TO DIGITAL CONVERTER WITH SERIAL CONTROL AND 8 ANALOG INPUTS MONOLITHIC SILICON.pdf)为本站会员(花仙子)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA DSCC-VID-V62 04618 REV A-2010 MICROCIRCUIT DIGITAL-LINEAR LOW VOLTAGE 10-BIT ANALOG TO DIGITAL CONVERTER WITH SERIAL CONTROL AND 8 ANALOG INPUTS MONOLITHIC SILICON.pdf

1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Update boilerplate paragraphs to current requirements. - ro 10-11-08 C. SAFFLE CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE R

2、EV A A A A A A PAGE 18 19 20 21 22 23 REV STATUS OF PAGES REV A A A A A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY TOM HESS TITLE MICROC

3、IRCUIT, DIGITAL-LINEAR, LOW VOLTAGE 10-BIT ANALOG TO DIGITAL CONVERTER WITH SERIAL CONTROL AND 8 ANALOG INPUTS, MONOLITHIC SILICON 03-11-14 APPROVED BY RAYMOND MONNIN SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04618 REV A PAGE 1 OF 23 AMSC N/A 5962-V073-10 Provided by IHSNot for ResaleNo reproduction

4、or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04618 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low voltage 10-bit analog to digital converter with

5、serial control and 8 analog inputs microcircuit, with an operating temperature range of -40C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the

6、item on the engineering documentation: V62/04618 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TLV1548 Low voltage 10 bit analog to digital converter with serial control and 8 analog inpu

7、ts 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 20 MO-150 Plastic small outline1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designat

8、or Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04618 REV A PAGE

9、3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) -0.5 V dc to +6.5 V dc 2/ Input voltage range (VI) (any input) . -0.3 V to VCC+0.3 V Output voltage range (VO) . -0.3 V to VCC+0.3 V Positive reference voltage, ( Vref +) . VCC+ 0.1 V Negative reference voltage, ( Vref - ) -0.1 V Peak inp

10、ut current II(any input) 20 mA Peak total input current (all inputs) . -30 mA Storage temperature range (TSTG) -65C to +150C Lead temperature 1, 6 mm (1/16 inch) from case for 10 seconds +260C Thermal resistance, junction-to-air (JA) 114.2C/W 1.4 Recommended operating conditions. 3/ Supply voltage r

11、ange (VCC) +2.7 V dc to +5.5 V dc Positive reference voltage, ( Vref+) VCC nominal 4/ Negative reference voltage, ( Vref-) . 0 V nominal4/ Differential reference voltage, ( Vref+-Vref-) +2.5 V dc to VCC + 0.2 V dc 4/ Analog input voltage range (VI) 0 to VCC4/ High level control input voltage, (VIH)

12、. 2.1 V dc minimum Low level control input voltage, (VIL) 0.6 V dc maximum Setup time, input data bits valid before I/O CLK, tsu (A) . 100 ns minimum Hold time, input data bits valid after I/O CLK, th(A) 5 ns minimum Setup time, CS to I/O CLK, tsu(CS) . 5 ns minimum 5/ Hold time, I/O CLK to CS , th(

13、CS) 65 ns minimum Pulse duration, FS high, twH(FS) 1 I/O CLK periods minimum 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those i

14、ndicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ All voltage values are with respect to GND with REF- and GND wired together (unless otherwise noted). 3/ Use of this product beyond t

15、he manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 4/ Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while inpu

16、t voltage less than that applied to REF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref +- Vref -); however, the electrical specifications are no longer applicable. 5/ To minimize errors caused by noise as CS the internal circuitry waits for a s

17、etup time after CS before responding to control input signals. No attempt should be made to clock in an input data until the minimum CS setup time has elapsed. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, O

18、HIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04618 REV A PAGE 4 1.4 Recommended operating conditions - continued. 3/ Pulse duration, CSTART , tw(CSTART) source impedance 1 k, VCC= 5.5 V . 0.84 s minimum Setup time, CS to CSTART , tsu(CSTART) 10 ns minimum Clock frequency at I/O CLK , fCLK; VCC= 5.5 V

19、 . 0.1 to 10 MHz VCC= 2.7 V . 0.1 to 2.81 MHz Pulse duration, I/O CLK high, twH(I/O); VCC= 5.5 V 50 ns minimum VCC= 2.7 V . 100 ns minimum Pulse duration, I/O CLK low, twL(I/O); VCC= 5.5 V . 50 ns minimum VCC= 2.7 V . 100 ns minimum Junction temperature (TJ) . 150C Operating free-air temperature ran

20、ge (TA) . -40C to +125C 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENT

21、S 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manuf

22、acturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The desig

23、n, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Truth table. The truth table shall be as shown in fi

24、gure 3. 3.5.4 Logic diagram. The logic diagram shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY

25、 CENTER COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04618 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCC= Vref+= 2.7 V to 5.5 V, I/O CLK frequency = 2.2 MHZTemperature, TADevice type Limits Unit Min Max High level output voltage VOHVCC

26、= 5.5 V, IOH= -0.2 mA -40C to +125C 01 2.4 V VCC= 2.7 V, IOH= -20 A 2.4 Low level output voltage VOLVCC= 5.5 V, IOH= 0.8 mA -40C to +125C 01 0.4 V VCC= 2.7 V, IOH= 20 A 0.1 High impedance output current IOZVO= VCC, CS = VCC-40C to +125C 01 2.5 A VO= 0, CS = VCC-2.5 High level input current IIHVI= VC

27、C-40C to +125C 01 2.5 A Low level input current IILVI= 0 -40C to +125C 01 2.5 A Operating supply current ICCVCC= 3.3 V to 5.5 V, conversion speed = fast, for all digital inputs, 0 VI 0.3 V or VI VCC 0.3 V -40C to +125C 01 1.5 mA VCC= 3.3 V to 5.5 V, conversion speed = slow, for all digital inputs, 0

28、 VI 0.3 V or VI VCC 0.3 V 1 VCC= 2.7 V to 3.3 V, conversion speed = slow, for all digital inputs, 0 VI 0.3 V or VI VCC 0.3 V 0.75 Extended sampling mode operating current ICC(ES)VCC= 3.3 V to 5.5 V 25C 01 1.5 typical mA VCC= 2.7 V to 3.3 V 1 typical Sustaining supply current ICC(ST)VCC= 2.7 V to 3.3

29、 V, conversion speed = slow, for all digital inputs, 0 VI 0.3 V or VI VCC 0.3 V 25C 01 0.3 typical mA See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 1

30、6236 DWG NO. V62/04618 REV A PAGE 6 TABLE I. Electrical performance characteristics continued. 1/ Test Symbol Conditions VCC= Vref+= 2.7 V to 5.5 V, I/O CLK frequency = 2.2 MHZTemperature, TADevice type Limits Unit Min Max Power down supply current ICC(PD)For all digital inputs, 0 VI 0.3 V or VI VCC

31、 0.3 V -40C to +125C 01 25 A Selected channel leakage current IIKGSelected channel at VCC, unselected channel at 0 V -40C to +125C 01 1 A Selected channel at 0 V, unselected channel at VCC-1 Maximum static analog reference current into REF+ Vref+= VCC= 5.5 V, Vref-= GND -40C to +125C 01 1 A Input ca

32、pacitance Ci Analog inputs -40C to +125C 01 55 pF Control inputs 15 Input multiplexer on resistance Zi VCC= 4.5 V -40C to +125C 01 1 k VCC= 2.7 V 5 Linearity error EL2/ -40C to +125C 01 1 LSB Differential linearity error ED3/ -40C to +125C 01 1 LSB Offset error EO3/ 4/ -40C to +125C 01 1.5 LSB Gain

33、error EG3/ 4/ -40C to +125C 01 1 LSB Total unadjusted error ET5/ -40C to +125C 01 1.75 LSB Self test output code DATA IN = 1011 6/ 25C 01 512 typical DATA IN = 1100 6/ 0 typical DATA IN = 1101 6 1023 typical Conversion time tconvFast conversion speed, see figure 5 -40C to +125C 01 10 s Slow conversi

34、on speed, See figure 5 25 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04618 REV A PAGE 7 TABLE I. Electrical performance characte

35、ristics continued. 1/ Test Symbol Conditions VCC= Vref+= 2.7 V to 5.5 V, I/O CLK frequency = 2.2 MHZTemperature, TADevice type Limits Unit Min Max Total cycle time (access, sample, conversion and EOC to CS delay tcFast conversion speed, 7/ 8/ 9/ see figure 5 -40C to +125C 01 10.1 + 10 I/O CLK s Slow

36、 conversion speed, 7/ 9/ see figure 5 40.1 +10 I/O CLK Channel acquisition time (sample) tacqSee figure 5 7/ -40C to +125C 01 6 I/O CLK periods Valid time, DATA OUT remains valid after I/O CLK tvSee figure 5 25C 01 20 typical ns Delay time, I/O CLK high to FS high td1(FS)See figure 5 -40C to +125C 0

37、1 5 50 ns Delay time, I/O CLK high to FS low td2(FS)See figure 5 -40C to +125C 01 10 60 ns Delay time, EOC to CS low td(EOC to CS ) See figure 5 10/ -40C to +125C 01 100 ns Delay time, CS to FS td(CS - FS) See figure 5 -40C to +125C 01 1 7 I/O CLK periods Delay time, 10thI/O CLK low to abort convers

38、ion td(I/O CS) See figure 5 11/ -40C to +125C 01 1.1 s Delay time, I/O CLK low to DATA OUT valid td(I/O-DATA) See figure 5 -40C to +125C 01 60 ns Delay time, 10 th I/O CLK to EOC low td(I/O-EOC) See figure 5 -40C to +125C 01 240 ns Enable time, CS low to DATA OUT valid (MSB driven) tPZH, tPZLSee fig

39、ure 5 -40C to +125C 01 1.3 s See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04618 REV A PAGE 8 TABLE I. Electrical performance chara

40、cteristics continued. 1/ Test Symbol Conditions VCC= Vref+= 2.7 V to 5.5 V, I/O CLK frequency = 2.2 MHZTemperature, TADevice type Limits Unit Min Max Disable time, CS high to DATA OUT invalid (high impedance) tPHZ, tPLZSee figure 5 -40C to +125C 01 150 ns Fall time, EOC tf(EOC) See figure 5 -40C to

41、+125C 01 50 ns Rise time, output data bus at 2.2 MHz I/O CLK tr(bus) See figure 5 -40C to +125C 01 250 ns Fall time, output data bus at 2.2 MHz I/O CLK tf(bus) See figure 5 -40C to +125C 01 250 ns 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure produ

42、ct performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Linearity

43、 error is the maximum deviation from the best straight line through the A/D transfer characteristics. 3/ Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltage less than that applied to REF- convert as all zeros (0000000000). The device is funct

44、ional with reference voltages down to 1 V (Vref+- Vref-); however, the electrical specifications are no longer applicable. 4/ Zero error is the difference between 0000000000 and the converted output for zero input voltage. Full-scale error is the difference between 1111111111 and the converted outpu

45、t for full-scale input voltage. 5/ Total unadjusted error comprises linearity, zero-scale and full-scale errors. 6/ Both the input data and the output codes are expressed in positive logic. 7/ I/O CLK period = 1/ (I/O CLK frequency). 8/ For 3.3 V to 5.5 V only. 9/ For microprocessor mode. 10/ For al

46、l operating modes. 11/ Any transactions of CS are recognized as valid only when the level is maintained for a setup time after the transition. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO SIZE A CODE I

47、DENT NO. 16236 DWG NO. V62/04618 REV A PAGE 9 Case X FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04618 REV A PAGE 10 Case X - continued. Symbol Dimensions Millimeters Inches Min Max Min Max A - 2.00 - .079 A1 0.05 - .002 - b 0.22 0.38 .008 .015 c 0.09 0.25 .003 .009 D 6.90 7.50 .272 .295 E 5.00 5.60 .197 .220 E1 7.40 8.20 .291 .323 e 0.65 BSC .026 BSC L 0.55 0.95 .022

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