DLA DSCC-VID-V62 04641 REV B-2013 MICROCIRCUIT DIGITAL-LINEAR SYNCHRONOUS PULSE WIDTH MODULATOR MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add a footnote to Table I. Add two footnotes to figure 1. Update boilerplate paragraph to current requirements. - ro 10-10-19 C. SAFFLE B Add device type 02. Table I, Line regulation and Load regulation tests, under conditions column, delete TJ= +125C and s

2、ubstitute TJ= +85C. Table I, Input offset TRACKIN test; under conditions column, delete 1.25 V and substitute 0.75 V; under limits column, delete -1.5 V, +1.5 V and substitute -2.5 V and +2.5 V. - ro 13-03-13 C. SAFFLE CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITI

3、ME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV B B B B B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Or

4、iginal date of drawing YY-MM-DD CHECKED BY TOM HESS TITLE MICROCIRCUIT, DIGITAL-LINEAR, SYNCHRONOUS PULSE WIDTH MODULATOR, MONOLITHIC SILICON 03-12-17 APPROVED BY RAYMOND MONNIN SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04641 REV B PAGE 1 OF 16 AMSC N/A 5962-V080-12 Provided by IHSNot for ResaleNo re

5、production or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04641 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance synchronous pulse width modulator (PWM)

6、microcircuit, with operating temperature ranges of -40C to +125C for device type 01 and -55C to +125C for device type 02. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number f

7、or identifying the item on the engineering documentation: V62/04641 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Temperature range Output voltage Circuit function 01 TPS54680-EP -40C to +125C 0.9 V to 3.3 V

8、 Synchronous pulse width modulator 02 TPS54680-EP -55C to +125C 0.9 V to 3.3 V Synchronous pulse width modulator 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 28 MO-153 Plastic small outline 1.2.3 Lead finishes. The lea

9、d finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license f

10、rom IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04641 REV B PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VI): VIN, ENA -0.3 V to 7 V RT -0.3 V to 6 V VSENSE, TRACKIN . -0.3 V to 4 V BOOT . -0.3 V to 17 V Output voltage range (VO): V

11、BIAS, COMP, PWRGD -0.3 V to 7 V PH -0.6 V to 10 V Source current (IO): PH Internally limited COMP, VBIAS 6 mA Sink current (IS): PH 12 A COMP 6 mA ENA, PWRGD 10 mA Voltage differential (AGND to PGND) 0.3 V Operating virtual junction temperature range (TJ): Device type 01 . -40C to +150C Device type

12、02 . -55C to +150C Storage temperature (TSTG) -65C to +150C 2/ Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds . +300C 1.4 Recommended operating conditions. 3/ Input voltage range (VI) . 3 V to 6 V Operating junction temperature (TJ) : Device type 01 . -40C to +125C Device type 02 . -55

13、C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.

14、Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Long term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. 3/ Use of this product beyond the manufacturers de

15、sign rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, C

16、OLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04641 REV B PAGE 4 1.5 Thermal information. Thermal metric Symbol Case X Unit Thermal resistance, junction-to-ambient 4/ JA36.1 C/W Thermal resistance, junction-to-case (top) 5/ JC(TOP)15.5 C/W Thermal resistance, junction-to-board 6/ JB

17、13.1 C/W Characterization parameter, junction-to-top 7/ JT0.4 C/W Characterization parameter, junction-to-board 8/ JB12.9 C/W Thermal resistance, junction-to-case (bottom) 9/ JC(BOTTOM)1.3 C/W 4/ The thermal resistance, junction-to-ambient under natural convection is obtained in a simulation on a JE

18、DEC standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. 5/ The thermal resistance, junction-to-case (top) is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI S

19、EMI standard G30-88. 6/ The thermal resistance, junction-to-board is obtained by simulating in an environment with a ring cold plate fixture to control the printed circuit board (PCB) temperature, as described in JESD51-8. 7/ Characterization parameter, junction-to-top (JT) estimates the junction te

20、mperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 8/ Characterization parameter, junction-to-board (JB) estimates the junction temperature of a device in a real system and is extracted from

21、the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 9/ The thermal resistance, junction-to-case (bottom) is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the

22、ANSI SEMI standard G30-88. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04641 REV B PAGE 5 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDE

23、C PUB 95 - Registered and Standard Outlines for Semiconductor Devices EIA/JESD 22 - Qualification Testing for Plastic Encapsulated Solid State Devices EIA/JESD 51-2a - Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) EIA/JESD 51-7 - High Effective Thermal

24、 Conductivity Test Board for Leaded Surface Mount Packages EIA/JESD 51-8 - Integrated Circuits Thermal Test Method Environment Conditions Junction-to-Board (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at

25、 http:/www.jedec.org) . American National Standards Institute ANSI SEMI STANDARD G30-88 - Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be addressed to the American National Standards Institute, Semiconductor Equipment and Mater

26、ials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. P

27、in 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance charac

28、teristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connecti

29、ons. The terminal connections shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16

30、236 DWG NO. V62/04641 REV B PAGE 6 TABLE I. Electrical performance characteristics. 1/ Test Symbol ConditionsTemperature, TJDevice type Limits Unit Min Max Supply voltage (VIN) section. Input voltage range VIN-40C to +125C 01 3.0 6.0 V -55C to +125C 02 3.0 6.0 Quiescent current IQfS= 350 kHz, RT ope

31、n, PH pin open -40C to +125C 01 15.8 mA -55C to +125C 02 15.8 fS= 500 kHz, RT 100 k, PH pin open -40C to +125C 01 23.5 -55C to +125C 02 23.5 Shutdown, ENA = 0 V -40C to +125C 01 1.4 -55C to +125C 02 1.4 Under voltage lock out section. Start threshold voltage -40C to +125C 01 3.0 V -55C to +125C 02 3

32、.0 Stop threshold voltage -40C to +125C 01 2.70 V -55C to +125C 02 2.70 Hysteresis voltage -40C to +125C 01 0.14 V -55C to +125C 02 0.093 Rising and falling edge deglitch 2/ -40C to +125C 01 2.5 typical s -55C to +125C 02 2.5 typical See footnotes at end of table. Provided by IHSNot for ResaleNo rep

33、roduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04641 REV B PAGE 7 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol ConditionsTemperature, TA Device type Limits Unit Min Max

34、 Bias voltage section. Output voltage, VBIAS I(VBIAS) = 0 -40C to +125C 01 2.70 2.90 V -55C to +125C 02 2.70 2.90 Output current, VBIAS 3/ -40C to +125C 01 100 A -55C to +125C 02 100 Cumulative reference section. Accuracy Vref-40C to +125C 01 0.882 0.900 V -55C to +125C 02 0.879 0.900 Regulation sec

35、tion. Line regulation 2/ IL= 3 A, fS= 350 kHz TJ= 85C 01, 02 0.04 %/V IL= 3 A, fS= 550 kHz 0.04 Load regulation 2/ IL= 0 A to 6 A, fS= 350 kHz TJ= 85C 01, 02 0.03 %/A IL= 0 A to 6 A, fS= 550 kHz 0.03 Supply voltage, VIN. Oscillator section. Internally set free running frequency RT open -40C to +125C

36、 01 280 450 kHz -55C to +125C 02 244 450 Externally set free running frequency range RT = 180 k -40C to +125C 01 252 308 kHz (1 % resistor to AGND) -55C to +125C 02 252 320 RT = 100 k -40C to +125C 01 460 540 (1 % resistor to AGND) -55C to +125C 02 432 540 RT = 68 k -40C to +125C 01 663 762 (1 % res

37、istor to AGND) -55C to +125C 02 656 762 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04641 REV B PAGE 8 TABLE I. Electrical perfo

38、rmance characteristics Continued. 1/ Test Symbol ConditionsTemperature, TJDevice type Limits Unit Min Max Oscillator section continued. Ramp valley 2/ -40C to +125C 01 0.75 typical V -55C to +125C 02 0.75 typical Ramp amplitude (peak-to-peak) 2/ -40C to +125C 01 1 typical V -55C to +125C 02 1 typica

39、l Minimum controllable on time 2/ -40C to +125C 01 200 ns -55C to +125C 02 230 Maximum duty cycle 2/ -40C to +125C 01 90 % -55C to +125C 02 90 Error amplifier section. Error amplifier open loop voltage gain 1 k COMP to AGND 2/ -40C to +125C 01 90 dB -55C to +125C 02 90 Error amplifier unity gain ban

40、dwidth Parallel 10 k, 2/ 160 pF COMP to AGND -40C to +125C 01 3 MHz -55C to +125C 02 3 Error amplifier common mode input voltage range Powered by internal LDO 2/ -40C to +125C 01 0 VBIAS V -55C to +125C 02 0 VBIAS Input bias current, VSENSE VSENSE = Vref-40C to +125C 01 250 nA -55C to +125C 02 300 S

41、ee footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04641 REV B PAGE 9 TABLE I. Electrical performance characteristics Continued. 1/ Test

42、 Symbol ConditionsTemperature, TJDevice type Limits Unit Min Max Error amplifier section continued. Output voltage slew rate (symmetric), COMP -40C to +125C 01 1.0 V/s -55C to +125C 02 1.4 typical PWM comparator section. PWM comparator propagation delay time, PWM comparator input to PH pin (excludin

43、g deadtime) 10 mV overdrive 2/ -40C to +125C 01 85 ns -55C to +125C 02 85 Enable section. Enable threshold voltage, ENA -40C to +125C 01 0.82 1.40 V -55C to +125C 02 0.82 1.40 Enable hysteresis voltage, ENA -40C to +125C 01 0.03 typical V -55C to +125C 02 0.03 typical Falling edge deglitch, ENA 2/ -

44、40C to +125C 01 2.5 typical s -55C to +125C 02 2.5 typical Leakage current, ENA VI= 5.5 V -40C to +125C 01 1 A -55C to +125C 02 1.6 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBU

45、S, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04641 REV B PAGE 10 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol ConditionsTemperature, TA Device type Limits Unit Min Max Power good section. Power good threshold voltage VSENSE falling -40C to +125C 01 90 typical %Vref-55

46、C to +125C 02 90 typical Power good hysteresis voltage 2/ -40C to +125C 01 3 typical %Vref-55C to +125C 02 3 typical Power good falling edge deglitch 2/ -40C to +125C 01 35 typical s -55C to +125C 02 35 typical Output saturation voltage, PWRGD I(sink)= 2.5 mA -40C to +125C 01 0.3 V -55C to +125C 02

47、0.3 Leakage current, PWRGD VI= 5.5 V -40C to +125C 01 1 A -55C to +125C 02 1 Current limit section. Current limit trip point VI= 3 V, output shorted 2/ -40C to +125C 01 7.2 A -55C to +125C 02 6.5 VI= 6 V, output shorted 2/ -40C to +125C 01 10 -55C to +125C 02 6.6 Current limit leading edge blanking time -40C to +125C 01 100 typical ns -55C to +125C 02 100 typical Current limit total response time -40C to +125C 01 200 typical ns -55C to +12