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本文(DLA DSCC-VID-V62 04644 REV A-2010 MICROCIRCUIT DIGITAL CMOS 3 3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149 1 (JTAG) TAP TRANSCEIVERS MONOLITHIC SILICON.pdf)为本站会员(boatfragile160)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA DSCC-VID-V62 04644 REV A-2010 MICROCIRCUIT DIGITAL CMOS 3 3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149 1 (JTAG) TAP TRANSCEIVERS MONOLITHIC SILICON.pdf

1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Update boilerplate paragraphs to current requirements. - PHN 10-04-06 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PR

2、EPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.milOriginal date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, CMOS, 3.3-V 10-BIT ADDRESSABLE SCAN PORTS, MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS, MONO

3、LITHIC SILICON YY-MM-DD 04-01-29 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04644 REV A PAGE 1 OF 13 AMSC N/A 5962-V040-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A

4、 CODE IDENT NO. 16236 DWG NO. V62/04644 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 3.3-V 10-bit addressable scan ports, multidrop-addressable IEEE Std 1149.1 (JTAG) TAP transceivers microcircuit, with an operating temperature range of -40C

5、to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04644 - 01 X E Drawing Device type Case outline Lea

6、d finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVT8996-EP 3.3-V 10-bit addressable scan ports, multidrop-addressable IEEE Std 1149.1 (JTAG) TAP transceivers 1.2.2 Case outline. The case outline are as specified herein. Outline le

7、tter Number of pins JEDEC PUB 95 Package style X 24 JEDEC MS-013 Plastic small-outline Y 24 JEDEC MO-153 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Ti

8、n-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04644 REV A PAGE 3 1.3 Absolute maximum ratings.

9、1/ Supply voltage range (VCC) . -0.5 V to +4.6 V Input voltage range (VI) . -0.5 V to 7.0 V 2/ Voltage range applied to any output in the high or power-off state (VO) -0.5 V to 7.0 V 2/ Current into any output in the low state (IO) . 128 mA Current into any output in the high state (IO) . 64 mA 3/ I

10、nput clamp current (IIK) (VIVCC. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. 5/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for p

11、roduct used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04644 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standa

12、rd Outlines for Semiconductor Devices JEDEC STD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org

13、) IEEE Standard 1149.1-1990 - Standard Test Access Port and Boundary Scan Architecture (Applications for copies should be addressed to the Institute of Electrical and Electronics Engineers, 445 Hoes Lane, Piscataway, NJ 08855-1331) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly

14、marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applic

15、able) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specif

16、ied herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Block diagram. The block diagram shall be as shown in figure 2. 3.5.3 Terminal connections. The terminal connections shall be as shown in figure 3. 3.5.4 Timing waveforms. The timing wavefor

17、ms shall be as shown in figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04644 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbo

18、l Test conditions -40C TA +85C Device type: All unless otherwise specified VCCLimits Unit Min Max Input clamp voltage VIKII= -18 mA 2.7 V -1.2 V High level output voltage VOHIOH= -100 A 2.7 V and 3.6 V VCC 0.2 V IOH= -8 mA 2.7 V 2.4 IOH= -32 mA 3.0 V 2.0 Low level output voltage VOLIOL= 100 A 2.7 V

19、0.2 V IOL= 24 mA 0.5 IOL= 16 mA 3.0 V 0.4 IOL= 32 mA 0.5 IOL= 64 mA 0.55 Input current IIVI= 5.5 V 0.0 V and 3.6 V 10 A PTCK VI= VCCor GND 3.6 V 1.0 High level input current IIHPTDI, PTMS, PTRSTnullnullnullnullnullnullnullnullnullVI= VCC3.6 V 1.0 A A9 A0, BYPnullnullnullnullnull, STDI VI= VCC3.6 V 1

20、.0 Low level input current IILPTDI, PTMS, PTRSTnullnullnullnullnullnullnullnullnullVI= GND 3.6 V -8.0 -30 A A9 A0, BYPnullnullnullnullnull, STDI VI= GND 3.6 V -25 -100 Input/output power-off leakage current IoffVIor VO= 0.0 V to 4.5 V 0.0 V 100 A Three-state output leakage current high IOZHPTDO, STD

21、O VO= 3.0 V 3.6 V 5.0 A Three-state output leakage current low IOZLPTDO, STDO VO= 0.5 V 3.6 V -5.0 A Three-state output leakage current power-up IOZPUVO= 0.5 V to 3.0 V 0.0 V to 1.5 V 100 A Three-state output leakage current power-down IOZPDVO= 0.5 V to 3.0 V 0.0 V to 1.5 V 100 A Quiescent supply cu

22、rrent ICCOff, STCK = H, STMS = H IO= 0.0 A VI= VCCor GND 3.6 V 2.0 On, PTDO = L, STCK = L, STDO = L, STMS = L 20 On, PTDO = H, STCK = H, STDO = H, STMS = H 7.0 TRST, STCK = L 10 Quiescent supply current delta, TTL input levels ICC2/ One input at VCC 0.6 V. Other inputs at VCCor GND. 3.0 V and 3.6 V

23、0.2 mA Input capacitance CIVI= 3.0 V or 0.0 V, TA= 25C 3.3 V 3.5 TYP pF Output capacitance COVO= 3.0 V or 0.0 V, , TA= 25C 3.3 V 6.5 TYP See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS CO

24、LUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04644 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions -40C TA +85C Device type: All unless otherwise specified VCCLimits Unit Min Max Clock frequency fclockPTCK See figure 4 2.7 V 20 MHz 3.0

25、 V and 3.6 V 25 Pulse duration twBYPnullnullnullnullnulllow 3/ 2.7 V and 3.6 V 8.0 ns PTCK high 20 PTCK low 12 PTRSTnullnullnullnullnullnullnullnullnulllow 9.0 Setup time tsuA9 A0 before PTCK 4/ 2.7 V and 3.6 V 10.2 PTDI before PTCK 10.1 PTMS before BYPnullnullnullnullnull 3/ 4.0 PTMS before PTCK 10

26、 Hold time thA9 A0 after PTCK 4/ 2.7 V and 3.6 V 4.0 PTDI after PTCK 4.0 PTMS after BYPnullnullnullnullnull 3/ 4.0 PTMS after PTCK 4.0 Maximum clock frequency, from PTCK fmaxSee figure 4 2.7 V 20 MHz 3.0 V and 3.6 V 25 Propagation delay time, BYPnullnullnullnullnull to CONnullnullnullnullnullnulltPL

27、H2.7 1.0 9.4 ns 3.0 V and 3.6 V 1.0 8.2 Propagation delay time, BYPnullnullnullnullnull to CONnullnullnullnullnullnulltPHL1.0 11.43.0 V and 3.6 V 1.0 9.8 Propagation delay time, BYPnullnullnullnullnull to STMS tPLH2.7 2.5 14.73.0 V and 3.6 V 2.5 12 tPHL2.5 13.43.0 V and 3.6 V 2.5 11.7 Propagation de

28、lay time, PTCK to STCK tPLH2.7 1.0 11.2 3.0 V and 3.6 V 1.0 9.6 tPHL1.0 11.8 3.0 V and 3.6 V 1.0 10 Propagation delay time, PTCK to CONnullnullnullnullnullnulltPLH2.7 3.5 24.8 3.0 V and 3.6 V 3.5 20.6 tPHL3.5 27.4 3.0 V and 3.6 V 3.5 23 Propagation delay time, PTCK (shadow-protocol acknowledge) to P

29、TDO tPLH2.7 3.0 17.4 3.0 V and 3.6 V 3.0 14.7 tPHL3.0 17.7 3.0 V and 3.6 V 3.0 15 Propagation delay time, PTCK (connect) to STMS tPLH5/ 2.7 V 5.5 23.9 3.0 V and 3.6 V 5.5 19.9 tPHL5/ 2.7 V 5.5 22.9 3.0 V and 3.6 V 5.5 19.1 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction o

30、r networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04644 REV A PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions -40C TA +85C Device type: All unless otherwise spe

31、cified VCCLimits Unit Min Max Propagation delay time, PTDI to STDO tPLHSee figure 4 2.7 V 1.0 9.9 ns 3.0 V and 3.6 V 1.0 8.3 tPHL2.7 1.0 10.2 3.0 V and 3.6 V 1.0 8.6 Propagation delay time, PTMS to STMS tPLH2.7 V 1.0 9.8 3.0 V and 3.6 V 1.0 8.5 tPHL2.7 1.0 10.3 3.0 V and 3.6 V 1.0 8.8 Propagation de

32、lay time, PTRSTnullnullnullnullnullnullnullnullnullto STRSTnullnullnullnullnullnullnullnulltPLH2.7 V 1.0 10 3.0 V and 3.6 V 1.0 8.4 tPHL2.7 1.0 10.5 3.0 V and 3.6 V 1.0 9.0 Propagation delay time, PTRSTnullnullnullnullnullnullnullnullnull to CONnullnullnullnullnullnulltPLH3.5 29 3.0 V and 3.6 V 3.5

33、23.9 Propagation delay time, PTRSTnullnullnullnullnullnullnullnullnull to STMS tPLH2.7 2.5 15.7 3.0 V and 3.6 V 2.5 13.2 Propagation delay time, STDI to PTDO tPLH2.7 V 1.0 8.2 3.0 V and 3.6 V 1.0 6.8 tPHL2.7 1.0 9.0 3.0 V and 3.6 V 1.0 7.6 Propagation delay time, BYPnullnullnullnullnull to PTDO tPZH

34、6/ 2.7 V 1.5 10.6 3.0 V and 3.6 V 1.5 9.0 tPZL2.7 1.5 11.9 3.0 V and 3.6 V 1.5 10.1 Propagation delay time, BYPnullnullnullnullnull to STDO tPZH7/ 2.7 V 1.5 9.3 3.0 V and 3.6 V 1.5 8.1 tPZL2.7 1.5 10.7 3.0 V and 3.6 V 1.5 9.2 Propagation delay time, PTCK to PTDO tPZH6/ 2.7 V 4.0 16.8 3.0 V and 3.6 V

35、 4.0 14.5 Propagation delay time, PTCK to STDO tPZH7/ 2.7 V 4.0 18.4 3.0 V and 3.6 V 4.0 15.8 tPZL2.7 4.0 19.1 3.0 V and 3.6 V 4.0 16.4 Propagation delay time, BYPnullnullnullnullnull to PTDO tPHZ6/ 2.7 V 1.5 9.3 3.0 V and 3.6 V 1.5 8.3 tPLZ2.7 1.5 8.3 3.0 V and 3.6 V 1.5 7.7 See footnotes at end of

36、 table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04644 REV A PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditi

37、ons -40C TA +85C Device type: All unless otherwise specified VCCLimits Unit Min Max Propagation delay time, BYPnullnullnullnullnull to STDO tPHZ7/ See figure 4 2.7 V 1.5 8.5 ns 3.0 V and 3.6 V 1.5 7.3 tPLZ2.7 1.5 7.1 3.0 V and 3.6 V 1.5 7.4 Propagation delay time, PTCK to PTDO tPHZ6/ 2.7 V 3.0 16.6

38、3.0 V and 3.6 V 3.0 14 tPLZ2.7 3.0 15.5 3.0 V and 3.6 V 3.0 13.9 Propagation delay time, PTCK to STDO tPHZ7/ 2.7 V 3.5 18.3 3.0 V and 3.6 V 3.5 16.9 tPLZ8/ 2.7 V 3.5 15.1 3.0 V and 3.6 V 3.5 13 Propagation delay time, PTRSTnullnullnullnullnullnullnullnullnull to PTDO tPHZ5/ 2.7 V 3.5 21.6 3.0 V and

39、3.6 V 3.5 18.3 tPLZ2.7 3.5 19.6 3.0 V and 3.6 V 3.5 19.3 Propagation delay time, PTRSTnullnullnullnullnullnullnullnullnull to STDO tPHZ6/ 2.7 V 4.5 21.4 3.0 V and 3.6 V 4.5 18.2 tPLZ2.7 4.5 23.4 3.0 V and 3.6 V 4.5 20.6 1/ Testing and other quality control techniques are used to the extent deemed ne

40、cessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/

41、or design. 2/ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCCor GND. 3/ In normal application of the ASP, such timing requirements with respect to BYP are met implicitly and, therefore, need not be considered. 4/ These requirements app

42、ly only in the case in which the address inputs are changed during a shadow protocol. For normal application of the ASP, it is recommended that the address inputs remain static throughout any shadow protocols. In such cases, the timing of address inputs relative to PTCK need not be considered. 5/ Th

43、e transitions at STMS are possible only when a shadow-protocol select is issued while STMS is held (in the OFF status) at a level that differs from that at PTMS. Such operation is not recommended since state synchronization of the primary TAP to secondary TAP cannot be ensured. 6/ In most applicatio

44、ns, the node to which PTDO is connected has a pullup resistor. In such cases, this parameter is not significant. 7/ In most applications, the node to which STDO is connected has a pullup resistor. In such cases, this parameter is not significant. 8/ This parameter applies only in case of protocol re

45、sult HARD ERROR. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04644 REV A PAGE 9 Case X Dimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max M

46、in Max Min Max Min Max A 0.104 2.65 E 0.291 0.299 7.39 7.59 A1 0.004 0.012 0.10 0.30 E1 0.400 0.419 10.15 10.65 b 0.014 0.020 0.35 0.51 e 0.050 NOM 1.27 NOM c 0.010 NOM 0.25 NOM L 0.016 0.050 0.40 1.27 D 0.600 0.610 15.24 15.49 NOTES: 1. This drawing is subject to change without notice. 2. Body dime

47、nsions do not include mold flash or protrusion not to exceed 0.006 inches (0.15 mm). 3. Falls within JEDEC MS-013. 4. All linear dimensions are shown in inches (millimeters). Metric equivalents are given for general information only. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproducti

48、on or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04644 REV A PAGE 10 Case Y Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A 1.20 0.047 E 4.30 4.50 0.169 0.177 A1 0.05 0.15 0.002 0.006 E1 6.20 6.60 0.244 0.260 b 0.1

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