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本文(DLA DSCC-VID-V62 04652 REV B-2012 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS QUADRUPLE 2-INPUT POSITIVE NAND GATE MONOLITHIC SILICON.pdf)为本站会员(diecharacter305)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA DSCC-VID-V62 04652 REV B-2012 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS QUADRUPLE 2-INPUT POSITIVE NAND GATE MONOLITHIC SILICON.pdf

1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Add device type 02. Update boilerplate. - CFS 07-04-09 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 12-04-10 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 432

2、18-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F.

3、Saffle TITLE MICROCIRCUIT, DIGITAL, LOW VOLTAGE CMOS, QUADRUPLE 2-INPUT POSITIVE NAND GATE, MONOLITHIC SILICON YY-MM-DD 04-03-08 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04652 REV A PAGE 1 OF 10 AMSC N/A 5962-V054-12 Provided by IHSNot for ResaleNo reproduction or networki

4、ng permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04652 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance quadruple 2-input positive NAND gate microcircuit, with an ope

5、rating temperature range of -40C to +125C for device type 01, and an operating temperature range of -55C to +125C for device type 02. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative cont

6、rol number for identifying the item on the engineering documentation: V62/04652 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device types. Device type Generic Circuit function 01 SN74LVC00A-EP Quadruple 2-input positive NAND gate 02 SN74LVC00

7、A- Quadruple 2-input positive NAND gate 1.2.2 Case outlines. The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 14 MS-012 Plastic small-outlineY 14 MO-153 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other l

8、ead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COL

9、UMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04652 REV B PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 6.5 V Input voltage range (VI) . -0.5 V to 6.5 V 2/ Output voltage range (VO) . -0.5 V to VCC+ 0.5 V 2/ 3/ Input clamp current (IIK) (VI 0) -50 mA Output cla

10、mp current (IOK) (VO 0) . -50 mA Continuous output current (IO) . 50 mA Continuous current through VCCor GND . 100 mA Package thermal impedance (JA): 4/ X package . 86C/W Y package . 113C/W Storage temperature range (TSTG) . -65C to 150C 1.4 Recommended operating conditions. 5/ Supply voltage range

11、(VCC): Operating 2.0 V to 3.6 V Data retention only 1.5 V minimum Minimum high level input voltage (VIH) (VCC= 2.7 V to 3.6 V) . 2.0 V Maximum low level input voltage (VIL) (VCC= 2.7 V to 3.6 V) 0.8 V Input voltage range (VI) . 0.0 V to 5.5 V Output voltage range (VO) . 0.0 V to VCCMaximum high leve

12、l output current (IOH): VCC= 2.7 V -12 mA VCC= 3.0 V -24 mA Maximum low level output current (IOL): VCC= 2.7 V 12 mA VCC= 3.0 V 24 mA Operating free-air temperature range (TA): Device type 01 . -40C to +125C Device type 02 . -55C to +125C 1/ Stresses beyond those listed under “absolute maximum ratin

13、gs” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may

14、affect device reliability. 2/ The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The value of VCCis provided in the recommended operating conditions table. 4/ The package thermal impedance is calculated in accordance with JE

15、SD 51-7. 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04652 REV

16、B PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at http:/www.je

17、dec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, o

18、r logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical perform

19、ance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outlines. The case outlines shall be as shown in 1.2.2 and figure 1. 3.5.2 Trut

20、h table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Test circuit and timing waveforms. The test circuit and timing waveforms shall be as

21、 shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04652 REV B PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions V

22、CCTemperature, TADevice type Limits Unit Min Max High level output voltage VOHIOH= -100 A 2.7 V to 3.6 V Device 01: 25C, -40C to 125C Device 02: 25C, -55C to 125C All VCC 0.2 V IOH= -12 mA 2.7 V 2.2 3.0 V 2.4 IOH= -24 mA 3.0 V 2.2 Low level output voltage VOLIOL= 100 A 2.7 V to 3.6 V 0.2 V IOL= 12 m

23、A 2.7 V 0.4 IOL= 24 mA 3.0 V 0.55 Input current IIVI= 5.5 V or GND 3.6 V 5 A Quiescent supply current ICCVI= VCCor GND IO= 0 A 3.6 V 10 A Quiescent supply current delta ICCOne input at VCC 0.6 V, Other inputs at VCCor GND 2.7 V to 3.6 V 500 A Input capacitance CiVI= VCCor GND 3.3 V 25C 5 TYP pF Powe

24、r dissipation capacitance per gate Cpdf = 10 MHz 2.5 V 18 TYP pF 3.3 V 19 TYP Propagation delay time, A or B to Y tpdSee figure 5. 2.7 V Device 01: 25C, -40C to 125C Device 02: 25C, -55C to 125C 5.1 ns 3.0 V to 3.6 V 1 4.3 1/ Testing and other quality control techniques are used to the extent deemed

25、 necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization a

26、nd/or design. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04652 REV B PAGE 6 Case X Dimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min

27、Max Min Max Min Max A - .069 - 1.75 E .150 0.157 3.81 4.00 A1 .004 .010 0.10 0.25 E1 .228 0.244 5.80 6.20 b .014 .020 0.35 0.51 e .050 BSC 1.27 BSC c .008 NOM 0.20 NOM L .016 0.044 0.40 1.12 D .337 .344 8.55 8.75 NOTES: 1. All linear dimensions are in inches (millimeters). 2. This case outline is su

28、bject to change without notice. 3. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 inches (0.15 mm). 4. Falls within JEDEC MS-012. FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CE

29、NTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04652 REV B PAGE 7 Case Y Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A - 1.20 - .047 E 4.30 4.50 .169 .177 A1 0.05 0.15 .002 .006 E1 6.20 6.60 .244 .260 b 0.19 0.30 .007 .012 e 0

30、.65 BSC .026 BSC c 0.15 NOM .006 NOM L 0.50 0.75 .020 .030 D 4.90 5.10 .193 .201 NOTES: 1. All linear dimensions are in millimeters (inches). 2. This case outline is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion, not to exceed 0.15 millimeters (0.006 in

31、). 4. Fall within JEDEC MO-153. FIGURE 1. Case outlines - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04652 REV B PAGE 8 (each gate) Inputs Output A

32、 B Y H H L L X H X L H H = High voltage level L = Low voltage level X = Immaterial FIGURE 2. Truth table. FIGURE 3. Logic diagram. Device type 01 and 02 Case outline X and Y Terminal number Terminal symbol Terminal number Terminal symbol 1 1A 8 3Y 2 1B 9 3A 3 1Y 10 3B 4 2A 11 4Y 5 2B 12 4A 6 2Y 13 4

33、B 7 GND 14 VCCFIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04652 REV B PAGE 9 NOTES: 1. CLincludes probe and jig capacitance. 2.

34、 All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO= 50 . 3. tPLHand tPHLare the same as tpd. 4. The outputs are measured one at a time with one input transition per measurement. FIGURE 5. Test circuit and timing waveforms. Provided by IHSNot for ResaleN

35、o reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04652 REV B PAGE 10 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test re

36、quirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeli

37、ng, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein

38、 is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply her

39、ein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top side marking V62/04652-01XE 01295 SN74LVC00AQDREP LVC00AE V62/04652-01YE 01295

40、SN74LVC00AQPWREP LVC00AEV62/04652-02YE 01295 SN74LVC00AMPWREP LVC00AM 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-

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