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本文(DLA DSCC-VID-V62 04659 REV A-2010 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR MULTIPLEXER MONOLITHIC SILICON.pdf)为本站会员(ownview251)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA DSCC-VID-V62 04659 REV A-2010 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR MULTIPLEXER MONOLITHIC SILICON.pdf

1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Update boilerplate paragraphs to current requirements. - PHN 10-04-06 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Charl

2、es F. Saffle DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.milOriginal date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, LOW VOLTAGE CMOS, QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER, MONOLITHIC SILICON YY-MM-DD 04-03-08 APPROVED BY Thom

3、as M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04659 REV A PAGE 1 OF 10 AMSC N/A 5962-V041-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04659 REV A PAG

4、E 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance quadruple 2-line to 1-line data selector/multiplexer microcircuit, with an operating temperature range of -40C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the i

5、tem of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04659 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic

6、Circuit function 01 SN74LVC157A-EP Quadruple 2-line to 1-line data selector/multiplexer 1.2.2 Case outlines. The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 MS-012 Plastic small-outlineY 16 MO-153 Plastic small-outline 1.2.3 Lead finishes. The

7、 lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license

8、from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04659 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 6.5 V Input voltage range (VI) . -0.5 V to 6.5 V 2/ Output voltage range (VO) . -0.5 V to VCC+ 0.5 V 2/ 3/ In

9、put clamp current (IIK) (VI 0) -50 mA Output clamp current (IOK) (VO 0) . -50 mA Continuous output current (IO) . 50 mA Continuous current through VCCor GND . 100 mA Package thermal impedance (JA): 4/ X package . 73C/W Y package . 108C/W Storage temperature range (TSTG) . -65C to 150C 1.4 Recommende

10、d operating conditions. 5/ 6/ Supply voltage range (VCC): Operating 2.0 V to 3.6 V Data retention only 1.5 V minimum Minimum high level input voltage (VIH) (VCC= 2.7 V to 3.6 V) . 2.0 V Maximum low level input voltage (VIL) (VCC= 2.7 V to 3.6 V) 0.8 V Input voltage range (VI) . 0.0 V to 5.5 V Output

11、 voltage range (VO) . 0.0 V to VCCMaximum high level output current (IOH): VCC= 2.7 V -12 mA VCC= 3.0 V -24 mA Maximum low level output current (IOL): VCC= 2.7 V 12 mA VCC= 3.0 V 24 mA Maximum input transition rise or fall rate (t/v) . 10 ns/V Operating free-air temperature range (TA) -40C to +125C

12、1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure t

13、o absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The value of VCCis provided in the recommended operating conditions table. 4/ The

14、package thermal impedance is calculated in accordance with JESD 51-7. 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. 6/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or d

15、istributor maintain no responsibility or liability for product used beyond the stated limits Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04659 REV A PAGE 4 2.

16、APPLICABLE DOCUMENTS JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard,

17、Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (option

18、al) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and ta

19、ble I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outlines. The case outlines shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3

20、.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Test circuit and timing waveforms. The test circuit and timing waveforms shall be as shown in figure 5. Provided by IHSNot for ResaleNo repro

21、duction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04659 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max High lev

22、el output voltage VOHIOH= -100 A 2.7 V to 3.6 V 25C, -40C to 125C All VCC 0.2 V IOH= -12 mA 2.7 V 2.2 3.0 V 2.4 IOH= -24 mA 3.0 V 2.2 Low level output voltage VOLIOL= 100 A 2.7 V to 3.6 V 0.2 V IOL= 12 mA 2.7 V 0.4 IOL= 24 mA 3.0 V 0.55 Input current IIAll inputs. VI= 5.5 V or GND 3.6 V 5 A Quiescen

23、t supply current ICCVI= VCCor GND IO= 0 A 3.6 V 10 A Quiescent supply current delta ICCOne input at VCC 0.6 V, Other inputs at VCCor GND 2.7 V to 3.6 V 500 A Input capacitance CiVI= VCCor GND 3.3 V 25C 5 TYP pF Power dissipation capacitance per gate Cpdf = 10 MHz 2.5 V 15 TYP pF 3.3 V 16 TYP Propaga

24、tion delay time, A or B to Y tpdSee figure 5. 2.7 V 25C, -40C to 125C 6.2 ns 3.3 V 0.3 V 0.8 5.4 Propagation delay time, A/B to Y 2.7 V 8.2 3.3 V 0.3 V 0.8 7 Propagation delay time, G to Y 2.7 V 7.8 3.3 V 0.3 V 0.8 6.5 1/ Testing and other quality control techniques are used to the extent deemed nec

25、essary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/o

26、r design. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04659 REV A PAGE 6 Case X Dimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max

27、Min Max Min Max A - 0.069 - 1.75 E 0.150 0.157 3.81 4.00 A1 0.004 0.010 0.10 0.25 E1 0.228 0.244 5.80 6.20 b 0.014 0.020 0.35 0.51 e 0.050 BSC 1.27 BSC c 0.008 NOM 0.20 NOM L 0.016 0.044 0.40 1.12 D 0.386 0.394 9.80 10.00 NOTES: 1. All linear dimensions are in inches (millimeters). 2. This case outl

28、ine is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 inches (0.15 mm). 4. Falls within JEDEC MS-012. FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE

29、SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04659 REV A PAGE 7 Case Y Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A - 1.20 - 0.047 E 4.30 4.50 0.169 0.177 A1 0.05 0.15 0.002 0.006 E1 6.20 6.60 0.244 0.260 b 0.19 0.

30、30 0.007 0.012 e 0.65 BSC 0.026 BSC c 0.15 NOM 0.006 NOM L 0.50 0.75 0.020 0.030 D 4.90 5.10 0.193 0.201 NOTES: 1. All linear dimensions are in millimeters (inches). 2. This case outline is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion, not to exceed 0.

31、15 millimeters (0.006 in). 4. Fall within JEDEC MO-153. FIGURE 1. Case outlines - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04659 REV A PAGE 8 Inp

32、ut Output GnullAnull/B A B Y H X X X L L L L X L L L H X H L H X L L L H X H H H = High voltage level L = Low voltage level X = Immaterial FIGURE 2. Truth table. FIGURE 3. Logic diagram. Device type 01 Case outlines: X and Y Terminal number Terminal symbol Terminal number Terminal symbol 1 Anull/B 9

33、 3Y 2 1A 10 3B 3 1B 11 3A 4 1Y 12 4Y 5 2A 13 4B 6 2B 14 4A 7 2Y 15 Gnull8 GND 16 VCCFIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62

34、/04659 REV A PAGE 9 NOTES: 1. CLincludes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO= 50 . 3. tPLHand tPHLare the same as tpd. 4. The outputs are measured one at a time with one input transition per measurement. FIGUR

35、E 5. Test circuit and timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04659 REV A PAGE 10 4. VERIFICATION 4.1 Product assurance requirements. The

36、 manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. P

37、REPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS

38、 class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source

39、(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top side mark

40、ing V62/04659-01XE 01295 SN74LVC157AQDREP C157AEP V62/04659-01YE 01295 SN74LVC157AQPWREP C157AEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-

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