DLA DSCC-VID-V62 04668 REV A-2010 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf

1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Update boilerplate paragraphs to current requirements. - PHN 10-05-25 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Charl

2、es F. Saffle DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.milOriginal date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, LOW VOLTAGE CMOS, OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, MONOLITHIC SILICON YY-MM-DD 04-03-18 APPROVED B

3、Y Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04668 REV PAGE 1 OF 10 AMSC N/A 5962-V053-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04668 REV A

4、 PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance octal edge-triggered D-type flip-flop with 3-state outputs microcircuit, with an operating temperature range of -40C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PI

5、N is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04668 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device typ

6、e Generic Circuit function 01 SN74LVC574A-EP Octal edge-triggered D-type flip-flop with 3-state outputs 1.2.2 Case outlines. The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 20 MS-013 Plastic small-outlineY 20 MO-153 Plastic small-outline 1.2.3 Le

7、ad finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium z Other Provided by IHSNot for ResaleNo reproduction or networking permitted

8、without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04668 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 6.5 V Input voltage range (VI) . -0.5 V to 6.5 V 2/ Voltage range applied to any output in th

9、e high-impedance or power-off state (VO) . -0.5 V to 6.5 V 2/ Voltage range applied to any output in the high or low state (VO) . -0.5 V to VCC+ 0.5 V 2/ 3/ Input clamp current (IIK) (VI 0) -50 mA Output clamp current (IOK) (VO 0) . -50 mA Continuous output current (IO) . 50 mA Continuous current th

10、rough VCCor GND . 100 mA Package thermal impedance (JA): 4/ X package . 58C/W Y package . 83C/W Storage temperature range (TSTG) . -65C to 150C 5/ 1.4 Recommended operating conditions. 6/ 7/ Supply voltage range (VCC): Operating 2.0 V to 3.6 V Data retention only 1.5 V minimum Minimum high level inp

11、ut voltage (VIH) (VCC= 2.7 V to 3.6 V) . 2.0 V Maximum low level input voltage (VIL) (VCC= 2.7 V to 3.6 V) 0.8 V Input voltage range (VI) . 0.0 V to 5.5 V Output voltage range (VO): High or low state 0.0 V to VCC3-state . 0.0 V to 5.5 V Maximum high level output current (IOH): VCC= 2.7 V -12 mA VCC=

12、 3.0 V -24 mA Maximum low level output current (IOL): VCC= 2.7 V 12 mA VCC= 3.0 V 24 mA Maximum input transition rise or fall rate (t/v) . 6 ns/V Operating free-air temperature range (TA) -40C to +125C 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the

13、 device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The inp

14、ut negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The value of VCCis provided in the recommended operating conditions table. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. 5/ Long-term high-temperatur

15、e storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. 6/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or l

16、iability for product used beyond the stated limits. 7/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A

17、CODE IDENT NO. 16236 DWG NO. V62/04668 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the

18、Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or

19、logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performan

20、ce characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outlines. The case outlines shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth

21、table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Test circuit and timing waveforms. The test circuit and timing waveforms shall be as s

22、hown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04668 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCC

23、Temperature TALimits Unit Min Max High level output voltage VOHIOH= -100 A 2.7 V to 3.6 V 25C, -40C to 125C VCC 0.2 V IOH= -12 mA 2.7 V 2.2 3.0 V 2.4 IOH= -24 mA 3.0 V 2.2 Low level output voltage VOLIOL= 100 A 2.7 V to 3.6 V 0.2 V IOL= 12 mA 2.7 V 0.4 IOL= 24 mA 3.0 V 0.55 Input current IIVI= 0 to

24、5.5 V 3.6 V 5 A Three-state output leakage current IOZVO= 0 to 5.5 V 3.6 V 15 A Quiescent supply current ICCVI= VCCor GND, IO= 0 A 3.6 V 10 A 3.6 V VI 5.5 V 2/ IO= 0 A 10Quiescent supply current delta ICCOne input at VCC 0.6 V, Other inputs at VCCor GND 2.7 V to 3.6 V 500 A Input capacitance CiVI= V

25、CCor GND 3.3 V 25C 4 TYP pF Output capacitance COVO= VCCor GND 3.3 V 5.5 TYP pF Power dissipation capacitance per latch CpdOutputs enabled f = 10 MHz 2.5 V 60 TYP pF 3.3 V 43 TYP Outputs disabled f = 10 MHz 2.5 V 9 TYP 3.3 V 15 TYP Maximum clock frequency fmaxSee figure 5 2.7 V 25C, -40C to 125C 150

26、 MHz 3.3 V 0.3 V 150Propagation delay time, CLK to Q tpd2.7 V 8 ns 3.3 V 0.3 V 1 7 Propagation delay time, output enable, OEnullnullnullnullto Q ten9 3.3 V 0.3 V 1 7.5 Propagation delay time, output disable, OEnullnullnullnullto Q tdis2.7 V 7 3.3 V 0.3 V 0.5 6.4 Clock frequency fclock2.7 V 150 MHz 3

27、3 V 0.3 V 150 Pulse duration, CLK high or low tw3.3 ns 3.3 V 0.3 V 3.3 Setup time, data before CLK tsu2.7 V 2 3.3 V 0.3 V 2 Hold time, data after CLK th3.3 V 0.3 V 2 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specif

28、ied temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ This applies in the disabled state only

29、 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04668 REV A PAGE 6 Case X Dimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max

30、Min Max A - 0.069 - 1.75 E 0.150 0.157 3.81 4.00 A1 0.004 0.010 0.10 0.25 E1 0.228 0.244 5.80 6.20 b 0.014 0.020 0.35 0.51 e 0.050 BSC 1.27 BSC c 0.008 NOM 0.20 NOM L 0.016 0.044 0.40 1.12 D 0.500 0.510 12.70 12.95 NOTES: 1. All linear dimensions are in inches (millimeters). 2. This case outline is

31、subject to change without notice. 3. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 inches (0.15 mm). 4. Falls within JEDEC MS-013. FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY

32、CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04668 REV A PAGE 7 Case Y Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A - 1.20 - 0.047 E 4.30 4.50 0.169 0.177 A1 0.05 0.15 0.002 0.006 E1 6.20 6.60 0.244 0.260 b 0.19 0.30 0.00

33、7 0.012 e 0.65 BSC 0.026 BSC c 0.15 NOM 0.006 NOM L 0.50 0.75 0.020 0.030 D 6.40 6.60 0.252 0.260 NOTES: 1. All linear dimensions are in millimeters (inches). 2. This case outline is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion, not to exceed 0.15 mill

34、imeters (0.006 in). 4. Fall within JEDEC MO-153. FIGURE 1. Case outlines - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04668 REV A PAGE 8 (each flip

35、flop) Inputs Output OEnullnullnullnullCLK D Q L H H L L L L L X Q0H X X Z H = High voltage level X = Immaterial L = Low voltage level Z = High-impedance state = Transition from low to high level. Q0= Level of Q before the indicated steady-state input conditions were established. FIGURE 2. Truth tab

36、le. FIGURE 3. Logic diagram. Device type 01 Case outlines: X and Y Terminal number Terminal symbol Terminal number Terminal symbol 1 OEnullnullnullnull11 CLK 2 1D 12 8Q 3 2D 13 7Q 4 3D 14 6Q 5 4D 15 5Q 6 5D 16 4Q 7 6D 17 3Q 8 7D 18 2Q 9 8D 19 1Q 10 GND 20 VCCFIGURE 4. Terminal connections. Provided

37、by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04668 REV A PAGE 9 NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions s

38、uch that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO= 50

39、 . 4. The outputs are measured one at a time with one input transition per measurement. 5. tPLZand tPHZare the same as tdis. 6. tPZLand tPZHare the same as ten. 7. tPLHand tPHLare the same as tpd. FIGURE 5. Test circuit and timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking

40、 permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04668 REV A PAGE 10 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in t

41、heir internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in

42、accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient cha

43、racteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed a

44、s a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top side marking V62/04668-01XE 01295 SN74LVC574AQDWREP C574AEP V62/04668-01YE 01295 SN74LVC574AQPWREP C574AEP

45、1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-