DLA DSCC-VID-V62 04672 REV A-2010 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 3 3-V ABT OCTAL BUFFER DRIVER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf

1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Update boilerplate paragraphs to current requirements. - PHN 10-05-25 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE

2、 SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.milOriginal date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED BIPOLAR CMOS, 3.3-V ABT OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS, MONOLITHIC SILICON YY-MM-DD 04-03-11 APPROVED BY Thomas M. Hess SIZE A

3、 CODE IDENT. NO. 16236 DWG NO. V62/04672 REV PAGE 1 OF 10 AMSC N/A 5962-V055-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04672 REV A PAGE 2 1. SCOPE 1.1 Sc

4、ope. This drawing documents the general requirements of a high performance 3.3-V ABT octal buffer/driver with 3-state outputs microcircuit, with an operating temperature range of -40C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification.

5、 The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04672 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN

6、74LVTH240-EP 3.3-V ABT octal buffer/driver with 3-state outputs 1.2.2 Case outline. The case outline are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 20 MO-153 Plastic small-outline1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes

7、 as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO S

8、IZE A CODE IDENT NO. 16236 DWG NO. V62/04672 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 4.6 V Input voltage range (VI) . -0.5 V to 7 V 2/ Voltage range applied to any output in the high-impedance or power-off state (VO) . -0.5 V to 7 V 2/ Voltage range appli

9、ed to any output in the high state (VO) . -0.5 V to VCC+ 0.5 V 2/ Current into any output in the low state (IO) . 128 mA Current into any output in the high state (IO) . 64 mA 3/ Input clamp current (IIK) (VI 0) -50 mA Output clamp current (IOK) (VO 0) . -50 mA Package thermal impedance (JA) . 83C/W

10、 4/ Storage temperature range (TSTG) . -65C to 150C 1.4 Recommended operating conditions. 5/ 6/ Supply voltage range (VCC) . 2.7 V to 3.6 V Minimum high level input voltage (VIH) 2.0 V Maximum low level input voltage (VIL) . 0.8 V Maximum input voltage (VI) . 5.5 V Maximum high level output current

11、(IOH) . -32 mA Maximum low level output current (IOL) . 64 mA Maximum input transition rise or fall rate (t/v) (Outputs enabled) 10 ns/V Minimum power-up ramp rate (t/VCC) 200 s/V Operating free-air temperature range (TA) -40C to +85C 1/ Stresses beyond those listed under “absolute maximum ratings”

12、may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affe

13、ct device reliability. 2/ The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3/ This current flows only when the output is in the high state and VO VCC. 4/ The package thermal impedance is calculated in accordance with JESD 51-7.

14、 5/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits 6/ All unused control inputs of the device must be held at VCCor GND to

15、ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04672 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 - Registered and Standard O

16、utlines for Semiconductor Devices JEDEC STD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3.

17、 REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked wi

18、th the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimensio

19、n. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figu

20、re 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Test circuit and timing waveforms. The test circuit and timing waveforms shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DE

21、FENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04672 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature TALimits Unit Min Max Input clamp voltage VIKII= -18 mA 2.7 V 25C, -40C to 85C -1.2 V High level output vo

22、ltage VOHIOH= -100 A 2.7 V to 3.6 V VCC 0.2 V IOH= -8 mA 2.7 V 2.4 IOH= -32 mA 3.0 V 2 Low level output voltage VOLIOL= 100 A 2.7 V 0.2 V IOL= 24 mA 0.5 IOL= 16 mA 3.0 V 0.4 IOL= 32 mA 0.5 IOL= 64 mA 0.55 Input current IIControl input. VI= 5.5 V 0 V or 3.6 V 10 A Control inputs. VI= VCCor GND 3.6 V

23、1 Data inputs., VI= VCCData inputs. , VI= 0 V -5 Input/output power-off leakage current IoffVIor VO= 0 to 4.5 V 0 V 100 A Input current (hold) II(hold)Data inputs. VI= 0.8 V 3 V 75 A Data inputs. VI= 2 V -75 Data inputs. VI= 0 V to 3.6 V 3.6 V 2/ +500 -750 3-state output current high IOZHVO= 3 V 3.6

24、 V 5 A 3-state output current low IOZLVO= 0.5 V 3.6 V -5 A 3-state output current power-up IOZPUVO= 0.5 V to 3 V OEnullnullnullnull= dont care 0 V to 1.5 V 100 A 3-state output current power-down IOZPDVO= 0.5 V to 3 V OEnullnullnullnull= dont care 1.5 V to 0 V 100 A Quiescent supply current ICCOutpu

25、ts high. VI= VCCor GND, IO= 0 A 3.6 V 0.19 mA Outputs low. VI= VCCor GND, IO= 0 A 7 Outputs disabled. VI= VCCor GND, IO= 0 A 0.19 Quiescent supply current delta ICC3/ One input at VCC 0.6 V, Other inputs at VCCor GND 3 V to 3.6 V 0.2 mA Input capacitance CiVI= 3 V or 0 V 3.3 V 25C 3 TYP pF Output ca

26、pacitance COVO= 3 V or 0 V 7 TYP pF See footnote at end of table Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04672 REV A PAGE 6 TABLE I. Electrical performance

27、 characteristics - Continued. 1/ Test Symbol Conditions VCCTemperature TALimits Unit Min Max Propagation delay time, A to Y tPLHCL= 50 pF See figure 5 2.7 V 25C, -40C to 85C 4.6 ns 3.3 V 0.3 V 1.1 3.8 tPHL2.7 V 4.23.3 V 0.3 V 1.3 4 Propagation delay time, output enable, OEnullnullnullnullto Y tPZH5.

28、63.3 V 0.3 V 1.1 4.6 tPZL2.7 V 5 3.3 V 0.3 V 1.4 4.4 Propagation delay time, output disable, OEnullnullnullnullto Y tPHZ4.63.3 V 0.3 V 2 4.4 tPLZ2.7 V 4.33.3 V 0.3 V 1.8 4.3 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the

29、 specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ This is the bus-hold maximum dyn

30、amic current. It is the minimum overdrive current required to switch the input from one state to another. 3/ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCCor GND. Provided by IHSNot for ResaleNo reproduction or networking permitted w

31、ithout license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04672 REV A PAGE 7 Case X Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A - 1.20 - 0.047 E 4.30 4.50 0.169 0.177 A1 0.05 0.15 0.002 0.00

32、6 E1 6.20 6.60 0.244 0.260 b 0.19 0.30 0.007 0.012 e 0.65 BSC 0.026 BSC c 0.15 NOM 0.006 NOM L 0.50 0.75 0.020 0.030 D 6.40 6.60 0.252 0.260 NOTES: 1. All linear dimensions are in millimeters (inches). 2. This case outline is subject to change without notice. 3. Body dimensions do not include mold f

33、lash or protrusion, not to exceed 0.15 millimeters (0.006 in). 4. Fall within JEDEC MO-153. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62

34、/04672 REV A PAGE 8 (each buffer) Inputs Output OEnullnullnullnullA Y L H H L L L H X Z H = High voltage level X = Immaterial L = Low voltage level Z = High-impedance state FIGURE 2. Truth table. FIGURE 3. Logic diagram. Device type 01 Case outlines: X and Y Terminal number Terminal symbol Terminal

35、number Terminal symbol 1 1OEnullnullnullnull11 2A12 1A1 12 1Y4 3 2Y4 13 2A24 1A2 14 1Y3 5 2Y3 15 2A36 1A3 16 1Y2 7 2Y2 17 2A48 1A4 18 1Y1 9 2Y1 19 2OEnullnullnullnull10 GND 20 VCCFIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from

36、 IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04672 REV A PAGE 9 NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform

37、2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO= 50 , tr 2.5 ns, and tf 2.5 ns. 4. The outputs are measured one at a time with one

38、input transition per measurement. FIGURE 5. Test circuit and timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04672 REV A PAGE 10 4. VERIFICATION

39、4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture

40、 sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic dischar

41、ge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as cha

42、nges are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAG

43、E code Vendor part number Top side marking V62/04672-01XE 01295 SN74LVTH240IPWREP LH240EP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-