DLA DSCC-VID-V62 04680 REV A-2010 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS 3 3-V ABT OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf

1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Update boilerplate paragraphs to current requirements. - PHN 10-08-10 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PR

2、EPARED BY Charles F. Saffle DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, LOW VOLTAGE CMOS, 3.3-V ABT OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS, MONOLITHIC SILICON YY-MM-DD 04-04-12 APPROVED BY Thomas

3、M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04680 REV A PAGE 1 OF 13 AMSC N/A 5962-V071-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04680 REV A PAGE 2 1. SCOPE

4、1.1 Scope. This drawing documents the general requirements of a high performance 3.3-V ABT octal bus transceiver and register with 3-state outputs microcircuit, with an operating temperature range of -40C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the it

5、em of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04680 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic C

6、ircuit function 01 SN74LVTH646-EP 3.3-V ABT octal bus transceiver and register with 3-state outputs 1.2.2 Case outline. The case outline are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 24 MO-153 Plastic small-outline1.2.3 Lead finishes. The lead finishes are as sp

7、ecified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AN

8、D MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04680 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 4.6 V Input voltage range (VI) . -0.5 V to 7 V 2/ Voltage range applied to any output in the high-impedance or power-off state (VO) . -0.5 V to

9、 7 V 2/ Voltage range applied to any output in the high state (VO) -0.5 V to VCC+0.5 V 2/ Current into any output in the low state (IO) . 128 mA Current into any output in the high state (IO) . 64 mA 3/ Input clamp current (IIK) (VI 0) -50 mA Output clamp current (IOK) (VO 0) . -50 mA Continuous out

10、put current (IO) . 50 mA Package thermal impedance (JA) . 88C/W 4/ Storage temperature range (TSTG) . -65C to 150C 1.4 Recommended operating conditions. 5/ 6/ Supply voltage range (VCC) . 2.7 V to 3.6 V Minimum high-level input voltage (VIH) 2.0 V Maximum low-level input voltage (VIL) . 0.8 V Maximu

11、m input voltage range (VI) . 5.5 V Maximum high level output current (IOH) . -32 mA Maximum low level output current (IOL) . 64 mA Maximum input transition rise or fall rate (t/v) (Outputs enabled) 10 ns/V Minimum power-up ramp rate (t/VCC) 200 s/V Operating free-air temperature range (TA) -40C to +

12、85C 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposu

13、re to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3/ This current flows only when the output is in the high state and VO VCC. 4/ The

14、package thermal impedance is calculated in accordance with JESD 51-7. 5/ All unused inputs of the device must be held at the associated VCCor GND to ensure proper device operation. 6/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufa

15、cturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04680 REV A PAGE

16、 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boule

17、vard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (

18、optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4,

19、and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Function table. The function table shall be as shown in f

20、igure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Test circuit and timing waveforms. The test circuit and timing waveforms shall be as shown in figure 5. Provided by IHSNot for Resa

21、leNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04680 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature TALimits Unit Min Max Input clamp voltage V

22、IKII= -18 mA 2.7 V 25C, -40C to 125C -1.2 V High level output voltage VOHIOH= -100 A 2.7 V to 3.6 V VCC 0.2 IOH= -8 mA 2.7 V 2.4 IOH= -32 mA 3 V 2 Low level output voltage VOLIOL= 100 A 2.7 V 0.2 V IOL= 24 mA 0.5 IOL= 16 mA 3.0 V 0.4 IOL= 32 mA 0.5 IOL= 64 mA 0.55 Input current IIControl inputs, VI=

23、 5.5 V 0 V or 3.6 V 10 Control inputs. VI= VCCor GND 3.6 V 1 A or B ports, VI= 5.5 V 2/ 20A or B ports, VI= VCC 2 1 A or B ports, VI= 0 V 2 -5 Input/output power-off leakage current IoffVIor VO= 0 to 4.5 V 0 V 100 A Input current (hold) II(hold)A or B ports, VI= 0.8 V 3 V 75 A or B ports, VI= 2 V -7

24、5 A or B ports. VI= 0 V to 3.6 V 3.6 V 3/ 500 3-state output current power-up IOZPUVO= 0.5 V to 3 V OEnullnullnullnull= dont care 0 V to 1.5 V 100 A 3-state output current power-down IOZPDVO= 0.5 V to 3 V OE = dont care 1.5 V to 0 V 100 A Quiescent supply current ICCOutputs high. VI= VCCor GND, IO=

25、0 A 3.6 V 0.19 mA Outputs low. VI= VCCor GND, IO= 0 A 5 Outputs disabled. VI= VCCor GND, IO= 0 A 0.19 Quiescent supply current delta ICC4/ One input at VCC 0.6 V, Other inputs at VCCor GND 3 V to 3.6 V 0.2 mA Input capacitance CiVI= 3 V or 0 V 3.3 V 25C 4 TYP pF Output capacitance CoVO= 3 V or 0 V 9

26、 TYP pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04680 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Tes

27、t Symbol Conditions VCCTemperature TALimits Unit Min Max Clock frequency fclock2.7 V 25C, -40C to 125C 150 MHz 3.3 V 0.3 V 150Pulse duration, CLK high or low twSee figure 5. 2.7 V 3.3 ns 3.3 V 0.3 V 3.3 Setup time, A or B before CLKAB or CLKBA tsuData high See figure 5. 2.7 V 1.5 3.3 V 0.3 V 1.2 Dat

28、a low See figure 5. 2.7 V 2.2 3.3 V 0.3 V 1.6 Hold time, A or B after CLKAB or CLKBA thSee figure 5. 2.7 V 0.8 3.3 V 0.3 V 0.8 Maximum clock frequency fmaxCL= 50 pF 2.7 V 150 MHz 3.3 V 0.3 V 150 Propagation delay time, CLKBA or CLKAB to A or B tPLH2.7 V 5.63.3 V 0.3 V 1.8 4.7 tPHL2.7 V 5.63.3 V 0.3

29、V 1.8 4.7 Propagation delay time, A or B to B or A tPLH2.7 V 4.13.3 V 0.3 V 1.3 3.5 tPHL2.7 V 4.13.3 V 0.3 V 1.3 3.5 Propagation delay time, SBA or SAB to A or B 5/ tPLH2.7 V 6 3.3 V 0.3 V 1.5 4.9 tPHL2.7 V 6 3.3 V 0.3 V 1.5 4.9 Propagation delay time, output enable, OEnullnullnullnullto A or B tPZH

30、2.7 V 6.53.3 V 0.3 V 1.1 5.2 tPZL2.7 V 6.53.3 V 0.3 V 1.1 5.2 Propagation delay time, output disable, OEnullnullnullnullto A or B tPHZ2.7 V 6.13.3 V 0.3 V 2.3 5.5 tPLZ2.7 V 5.93.3 V 0.3 V 2.3 5.5 Propagation delay time, output enable, DIR to A or B tPZH2.7 V 6.63.3 V 0.3 V 1.3 5.2 tPZL2.7 V 6.63.3 V

31、 0.3 V 1.3 5.2 Propagation delay time, output disable, DIR to A or B tPHZ2.7 V 6.73.3 V 0.3 V 1.5 5.6 tPLZ2.7 V 6.33.3 V 0.3 V 1.5 5.6 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO

32、 SIZE A CODE IDENT NO. 16236 DWG NO. V62/04680 REV A PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not nece

33、ssarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Unused terminals at VCCor GND. 3/ This is the bus-hold maximum dynamic current. It

34、 is the minimum overdrive current required to switch the input from one state to another. 4/ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCCor GND. 5/ These parameters are measured with the internal output state of the storage registe

35、r opposite that of the bus input. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04680 REV A PAGE 8 Case X Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Mi

36、n Max Min Max Min Max Min Max A - 1.20 - 0.047 E 4.30 4.50 0.169 0.177 A1 0.05 0.15 0.002 0.006 E1 6.20 6.60 0.244 0.260 b 0.19 0.30 0.007 0.012 e 0.65 BSC 0.026 BSC c 0.15 NOM 0.006 NOM L 0.50 0.75 0.020 0.030 D 7.70 7.90 0.303 0.311 NOTES: 1. All linear dimensions are in millimeters (inches). 2. T

37、his case outline is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion, not to exceed 0.15 millimeters (0.006 in). 4. Fall within JEDEC MO-153. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from

38、IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04680 REV A PAGE 9 Inputs Data I/Os Operation or Function OE DIR CLKAB CLKBA SAB SBA A1-A8 B1-B8 X X X X X X X X X X Input Unspecified * Unspecified * Input Store A, B unspecified * Store B, A unspecified * H H X X

39、H or L H or L X X X X Input Input disabled Input Input disabled Store A and B data Isolation, hold storage L L L L X X X H or L X X L H Output Output Input Input Real-time B data to A bus Stored B data to A bus L L H H X H or L X X L H X X Input Input Output Output Real-time A data to B bus Stored A

40、 data to B bus * The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. H = High voltage level L = Low voltage level X = Immaterial

41、= Low-to-high transition FIGURE 2. Function table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04680 REV A PAGE 10 OE DIR CLKAB CLKBA SAB SBA OE DIR CLKAB CLKBA SAB SBA

42、L L X X X L L H X X L X REAL-TIME TRANSFER REAL-TIME TRANSFER BUS B TO BUS A BUS A TO BUS B OE DIR CLKAB CLKBA SAB SBA OE DIR CLKAB CLKBA SAB SBA X X H X X X X X X X X X X X L L L H X L L X X H H X STORAGE FROM TRANSFER STORED DATA A, B, OR A AND B TO A AND/OR B FIGURE 2. Function table - Continued.

43、 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04680 REV A PAGE 11 FIGURE 3. Logic diagram. Device type 01 Case outlines: X Terminal number Terminal symbol Terminal number

44、 Terminal symbol 1 CLKAB 13 B8 2 SAB 14 B7 3 DIR 15 B6 4 A1 16 B5 5 A2 17 B4 6 A3 18 B3 7 A4 19 B2 8 A5 20 B1 9 A6 21 OEnullnullnullnull10 A7 22 SBA 11 A8 23 CLKBA 12 GND 24 VCCFIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from I

45、HS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04680 REV A PAGE 12 NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an

46、 output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO= 50 , tr 2.5 ns, tf 2.5 ns. 4. The outputs are measured one at a time with one input transitio

47、n per measurement. FIGURE 5. Test circuit and timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04680 REV A PAGE 13 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and lab