DLA DSCC-VID-V62 04697 REV A-2011 MICROCIRCUIT DIGITAL HIGH SPEED CMOS HEX INVERTER TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf

1、 REVISIONSLTR DESCRIPTION DATE (YY-MM-DD) APPROVEDA Update boilerplate paragraphs to current requirements. - PHN 11-02-01 David J. Corbett CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item

2、 drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A PAGE 1 2 3 4 5 6 7 8 PMIC N/A PREPARED BY Thanh V. Nguyen DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Thanh V. Nguyen TITLE MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS, HEX INVERTER, TTL CO

3、MPATIBLE INPUTS, MONOLITHIC SILICON YY-MM-DD 04-04-13 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04697 REV A PAGE 1 OF 8 AMSC N/A 5962-V030-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS CO

4、LUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04697 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance hex inverter microcircuit, with an operating temperature range of -40C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The

5、 manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04697 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device ty

6、pe(s). Device type Generic Circuit function 01 74HCT04-EP Hex inverter, TTL compatible inputs 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 14 MS-012 Plastic small-outline package 1.2.3 Lead finishes. The lead finishes ar

7、e as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 7.0 V Input clamp current (IIK) (VI 0

8、or VI VCC) . 20 mA 2/ Output clamp current (IOK) (VO 0 or VO VCC) . 20 mA 2/ Continuous output current (IO) (VO= 0 to VCC) 25 mA Continuous current through VCCor GND . 50 mA Storage temperature range (TSTG) . -65C to 150C Package thermal impedance (JA): 3/ X package . 86C/W _ 1/ Stresses beyond thos

9、e listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated

10、 conditions for extended periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The package thermal impedance is calculated in accordance with JESD 51-7. Provided by IHSNot for ResaleNo reproduction or n

11、etworking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04697 REV A PAGE 3 1.4 Recommended operating conditions. 4/ 5/ Supply voltage range (VCC) . 4.5 V to 5.5 V Input voltage range (VI) . 0.0 V to VCC Output voltage ra

12、nge (VO) . 0.0 V to VCCMinimum high level input voltage (VIH): VCC= 4.5 V to 5.5 V . 2.0 V Maximum low level input voltage (VIL): VCC= 4.5 V to 5.5 V . 0.8 V Maximum input transition rise or fall time (t/v). 500 ns Operating free-air temperature range (TA) -40C to +85C 2. APPLICABLE DOCUMENTS JEDEC

13、PUB 95 - Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 3103 North 10thSt., Suite 240-S, Arlington, VA 222

14、01-2107 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit cont

15、ainer. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4

16、 Design, construction, and physical dimensions. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic d

17、iagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Test circuit and timing waveforms. The test circuit and timing waveforms shall be as shown in figure 5. 4/ All unused inputs of the device must be held a

18、t VCCor GND to ensure proper device operation. 5/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for Re

19、saleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04697 REV A PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCC Temperature, TA Device type Limits Unit Mi

20、n Max High level output voltage VOH VI= VIHor VIL2/ IOH= -20 A 4.5 V 25C, -40C to 85C All 4.4 V VI= VIHor VIL2/ IOH= -4 mA 4.5 V 25C 3.98 -40C to 85C 3.84 Low level output voltage VOL VI= VIHor VIL2/ IOL= 20 A 4.5 V 25C, -40C to 85C All 0.1 V VI= VIHor VIL2/ IOL= 4 mA 4.5 V 25C 0.26 -40C to 85C 0.33

21、 Input current II VI= VCCor 0 V 5.5 V 25C All 100 nA -40C to 85C 1000 Quiescent supply current ICC VI= VCCor 0 V IO= 0 A 5.5 V 25C All 2.0 A -40C to 85C 20.0 Quiescent supply current delta, TTL input levels ICC3/ One input at 0.5 V or 2.4 V Other inputs at 0.0 V or VCC5.5 V 25C All 2.4 mA -40C to 85

22、C 2.9 Input capacitance CI 4.5 V to 5.5 V 25C, -40C to 85C All 10 pF Power dissipation capacitance per inverter CPD No load 25C All 20 typical pF Propagation delay time, A to Y tpd CL= 50 pF See figure 5 4.5 V 25C All 20 ns -40C to 85C 25 5.5 V 25C 18 -40C to 85C 23 Output transition time tt 4.5 V 2

23、5C All 15 ns -40C to 85C 19 5.5 V 25C 14 -40C to 85C 17 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all paramete

24、rs may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ The values to be used for VIHand VILshall be the VIHminimum and VILmaximum values listed in section 1.4 herein. 3/ This is the increase in supply curr

25、ent for each input that is at one of the specified TTL voltage levels, rather than 0.0 V or VCC. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04697 REV A PAGE 5

26、 Case X Dimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max A .069 1.75 E .150 .157 3.81 4.00 A1 .004 .010 0.10 0.25 E1 .228 .244 5.80 6.20 b .014 .020 0.35 0.51 e .050 BSC 1.27 BSC c .008 NOM 0.20 NOM L .016 .044 0.40 1.12 D .337 .344 8.55 8.75 NOTES: 1. A

27、ll linear dimensions are in inches (millimeters). 2. This case outline is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion, not to exceed .006 inches (0.15 millimeters). 4. Fall within JEDEC MS-012. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo r

28、eproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04697 REV A PAGE 6 Each inverter Input A Output Y H L L H H = High voltage level L = Low voltage level FIGURE 2. Truth table. FIGURE 3. Logic diagra

29、m. Device type 01 Case outlines: X Terminal number Terminal symbol Terminal number Terminal symbol 1 1A 8 4Y 2 1Y 9 4A 3 2A 10 5Y 4 2Y 11 5A 5 3A 12 6Y 6 3Y 13 6A 7 GND 14 VCCFIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS

30、-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04697 REV A PAGE 7 NOTES: 1. CLincludes probe and test-fixture capacitance. 2. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following c

31、haracteristics: PRR 1 MHz, ZO= 50 , tr= 6 ns, tf= 6 ns. 3. The outputs are measured one at a time with one input transition per measurement. 4. tPLHand tPHLare the same as tpd. FIGURE 5. Test circuit and timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without l

32、icense from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04697 REV A PAGE 8 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documen

33、tation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the m

34、anufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the d

35、evice manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of pres

36、ent or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top side marking V62/04697-01XE 01295 SN74HCT04IDREP SHCT04IEP 1/ The vendor item drawing establishes an administrative control numb

37、er for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-