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本文(DLA DSCC-VID-V62 04719 REV A-2011 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 3 3-V ABT 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf)为本站会员(sofeeling205)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA DSCC-VID-V62 04719 REV A-2011 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 3 3-V ABT 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf

1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Update boilerplate paragraphs to current requirements. - PHN 11-07-22 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV

2、PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED BIPOLAR CMOS, 3.3-V ABT 16-BIT RE

3、GISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, MONOLITHIC SILICON YY-MM-DD 04-05-04 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04719 REV A PAGE 1 OF 11 AMSC N/A 5962-V062-11 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENS

4、E SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04719 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 3.3-V ABT 16-bit registered transceiver with 3-state outputs microcircuit, with an operating temperature range

5、 of -40C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04719 - 01 X E Drawing Device type Case ou

6、tline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVTH16952-EP 3.3-V ABT 16-bit registered transceiver with 3-state outputs 1.2.2 Case outline. The case outline is as specified herein. Outline letter Number of pins JEDEC PU

7、B 95 Package style X 56 MO-153 Plastic small-outline1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided

8、by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04719 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 4.6 V Input voltage range (VI) .

9、-0.5 V to 7 V 2/ Voltage range applied to any output in the high-impedance or power-off state (VO) . -0.5 V to 7 V 2/ Voltage range applied to any output in the high state (VO) . -0.5 V to VCC+ 0.5 V 2/ Current into any output in the low state (IO) . 128 mA Current into any output in the high state

10、(IO) . 64 mA 3/ Input clamp current (IIK) (VI 0) -50 mA Output clamp current (IOK) (VO 0) . -50 mA Package thermal impedance (JA) . 64C/W 4/ Storage temperature range (TSTG) . -65C to 150C 1.4 Recommended operating conditions. 5/ Supply voltage range (VCC) . 2.7 V to 3.6 V Minimum high level input v

11、oltage (VIH) 2 V Maximum low level input voltage (VIL0.8 V Maximum input voltage (VI) . 5.5 V Maximum high level output current (IOH) . -32 mA Maximum low level output current (IOL) . 64 mA Maximum input transition rise or fall rate (t/v) (Outputs enabled) 10 ns/V Minimum power-up ramp rate (t/VCC)

12、200 s/V Operating free-air temperature range (TA) -40C to +85C 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packa

13、ges (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are

14、stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output negat

15、ive-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3/ This current flows only when the output is in the high state and VO VCC. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. 5/ All unused control inputs of the device must be

16、held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04719 REV A PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be

17、 permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with

18、 items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical

19、 dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Function table. The function table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. T

20、he terminal connections shall be as shown in figure 4. 3.5.5 Test circuit and timing waveforms. The test circuit and timing waveforms shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUM

21、BUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04719 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max Input clamp voltage VIKII= -18 mA 2.7 V 25C, -40C to 85C All -1.2 V High level output voltage VOHIOH= -100

22、 A 2.7 V to 3.6 V VCC 0.2 V IOH= -8 mA 2.7 V 2.4 IOH= -32 mA 3 V 2 Low level output voltage VOLIOL= 100 A 2.7 V 0.2 V IOL= 24 mA 0.5 IOL= 16 mA 3 V 0.4 IOL= 32 mA 0.5 IOL= 64 mA 0.55 Input current IIControl inputs. VI= VCCor GND 3.6 V 1 A Control inputs., VI= 5.5 V 0 V or 3.6 V 10 A or B ports, VI=

23、5.5 V 2/ 3.6 V 20 A or B ports, VI= VCC2/ 1 A or B ports, VI= 0 V 2 -5 Input/output power-off leakage current IoffVIor VO= 0 V to 4.5 V 0 V 100 A Input current (hold) II(hold)A or B ports, VI= 0.8 V 3 V 75 AA or B ports, VI= 2 V -75 A or B ports. VI= 0 V to 3.6 V 3/ 3.6 V 500 3-state output current

24、power-up IOZPUVO= 0.5 V to 3 V OE = dont care 0 V to 1.5 V 100 A 3-state output current power-down IOZPDVO= 0.5 V to 3 V OE = dont care 1.5 V to 0 V 100 A Quiescent supply current ICCOutputs high. VI= VCCor GND, IO= 0 A 3.6 V 0.19 mA Outputs low. VI= VCCor GND, IO= 0 A 5 Outputs disabled. VI= VCCor

25、GND, IO= 0 A 0.19 Quiescent supply current delta ICC4/ One input at VCC 0.6 V, Other inputs at VCCor GND 3 V to 3.6 V 0.2 mA Input capacitance CiVI= 3 V or 0 V 3.3 V 25C 4 TYP pF Input/output capacitance CioVO= 3 V or 0 V 10 TYP pF See footnotes at end of table. Provided by IHSNot for ResaleNo repro

26、duction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04719 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max

27、 Clock frequency fclock2.7 V 25C, -40C to 85C All 150 MHz 3.3 V 0.3 V 150 Pulse duration, CLK high or low twSee figure 5. 2.7 V 3.3 ns 3.3 V 0.3 V 3.3 Setup time, A or B before CLK tsu2.7 V 2.5 ns 3.3 V 0.3 V 1.7 Setup time, CLKEN before CLK 2.7 V 2.8 ns 3.3 V 0.3 V 2 Hold time, A or B after CLK th2

28、.7 V 0 ns 3.3 V 0.3 V 0.8 Hold time, CLKEN after CLK 2.7 V 0 ns 3.3 V 0.3 V 0.4 Maximum frequency fmaxCL= 50 pF 2.7 V 150 MHz 3.3 V 0.3 V 150 Propagation delay time, CLKBA or CLKAB to A or B tPLHCL= 50 pF See figure 5. 2.7 V 4.4 ns 3.3 V 0.3 V 1.3 4 tPHL2.7 V 4.43.3 V 0.3 V 1.3 4 Propagation delay t

29、ime, output enable, OEBA or OEAB to A or B tPZH2.7 V 4.93.3 V 0.3 V 1 4 tPZL2.7 V 4.93.3 V 0.3 V 1 4 Propagation delay time, output disable, OEBA or OEAB to A or B tPHZ2.7 V 6.23.3 V 0.3 V 2.1 5.7 tPLZ2.7 V 5.33.3 V 0.3 V 2.1 5.1 1/ Testing and other quality control techniques are used to the extent

30、 deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characteriz

31、ation and/or design. 2/ Unused pins at VCCor GND. 3/ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. 4/ This is the increase in supply current for each input that is at the specified TTL voltage level, rather t

32、han VCCor GND. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04719 REV A PAGE 7 Case X Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min

33、 Max Min Max Min Max A - 1.20 - 0.047 E 4.30 4.50 0.169 0.177 A1 0.05 0.15 0.002 0.006 E1 6.20 6.60 0.244 0.260 b 0.19 0.30 0.007 0.012 e 0.65 BSC 0.026 BSC c 0.15 NOM 0.006 NOM L 0.50 0.75 0.020 0.030 D 6.40 6.60 0.252 0.260 NOTES: 1. All linear dimensions are in millimeters (inches). 2. This case

34、outline is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion, not to exceed 0.15 millimeters (0.006 in). 4. Fall within JEDEC MO-153. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-D

35、EFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04719 REV A PAGE 8 Function Table 1/ Inputs Output B CLKENAB CLKAB OEAB A H X L L X X L X L L L L H X X L L X B02/ B02/ L H Z H = High voltage level Z = High impedance state L = Low voltage level = Low-to-high tran

36、sition X = Immaterial 1/ A-to-B data flow is shown; B-to-A flow is similar, but uses CLKENBA, CLKBA, and OEBA. 2/ Level of B before the indicated steady-state input conditions were established. FIGURE 2. Function table. FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or network

37、ing permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04719 REV A PAGE 9 Device type 01 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 1OEAB 29 2OEBA 2 1CLKAB 30 2CLKBA 3 1CLKENAB 31 2CLKENB

38、A4 GND 32 GND 5 1A1 33 2B8 6 1A2 34 2B77 VCC35 VCC8 1A3 36 2B69 1A4 37 2B5 10 1A5 38 2B411 GND 39 GND 12 1A6 40 2B3 13 1A7 41 2B214 1A8 42 2B1 15 2A1 43 1B816 2A2 44 1B7 17 2A3 45 1B618 GND 46 GND 19 2A4 47 1B5 20 2A5 48 1B421 2A6 49 1B3 22 VCC50 VCC23 2A7 51 1B224 2A8 52 1B1 25 GND 53 GND 26 2CLKEN

39、AB 54 1CLKENBA 27 2CLKAB 55 1CLKBA28 2OEAB 56 1OEBA FIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04719 REV A PAGE 10 NOTES: 1. C

40、Lincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All in

41、put pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO= 50 , tr 2.5 ns, and tf 2.5 ns. 4. The outputs are measured one at a time with one input transition per measurement. FIGURE 5. Test circuit and timing waveforms. Provided by IHSNot for ResaleNo reproduction or

42、 networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04719 REV A PAGE 11 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as ind

43、icated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking s

44、hall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the

45、salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be

46、construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top side marking V62/04719-01XE 01295 CLVTH16952IDGGREP LH16952EP 1/ The vendor item drawing establi

47、shes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-

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