DLA DSCC-VID-V62 04724 REV A-2011 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS 16-BIT BUFFER DRIVER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 11-08-22 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing RE

2、V PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, LOW VOLTAGE CMOS, 16-BIT BUFF

3、ER/DRIVER WITH 3-STATE OUTPUTS, MONOLITHIC SILICON YY-MM-DD 04-06-09 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04724 REV A PAGE 1 OF 11 AMSC N/A 5962-V069-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CEN

4、TER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04724 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 16-bit buffer/driver with 3-state outputs microcircuit, with an operating temperature range of -40C to +85C. 1.2 Vendor It

5、em Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04724 - 01 X E Drawing Device type Case outline Lead finish number (See 1

6、.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVC16244A-EP 16-bit buffer/driver with 3-state outputs 1.2.2 Case outlines. The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 48 JEDEC MO-153 Plastic sm

7、all-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction o

8、r networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04724 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to +6.5 V Input voltage range (VI) . -0.5 V to 6.5 V 2/ Voltage range app

9、lied to any output in the high-impedance or power-off state (VO) . -0.5 V to 6.5 V 2/ Voltage range applied to any output in the high or low state (VO) . -0.5 V to VCC+ 0.5 V 2/ 3/ Input clamp current (IIK) (VI 0) 50 mA Output clamp current (IOK) (VO 0) . 50 mA Continuous output current (IO) . 50 mA

10、 Continuous current through each VCCor GND 100 mA Package thermal impedance (JA) . 70C/W 4/ Storage temperature range (TSTG) . -65C to +150C 1.4 Recommended operating conditions. 5/ Supply voltage range (VCC): Operating . 1.65 V to 3.6 V Data retention only 1.5 V Minimum high level input voltage (VI

11、H): VCC= 1.65 V to 1.95 V . 0.65 x VCCVCC= 2.3 V to 2.7 V . 1.7 V VCC= 2.7 V to 3.6 V . 2 V Maximum low level input voltage (VIL): VCC= 1.65 V to 1.95 V . 0.35 x VCCVCC= 2.3 V to 2.7 V . 0.7 V VCC= 2.7 V to 3.6 V . 0.8 V Input voltage range (VI) . 0 V to 5.5 V Output voltage range (VO): High or low

12、state 0 V to VCC3-state . 0 V to 5.5 V Maximum high level output current (IOH): VCC= 1.65 V -4 mA VCC= 2.3 V -8 mA VCC= 2.7 V -12 mA VCC= 3 V . -24 mA Maximum low level output current (IOL): VCC= 1.65 V 4 mA VCC= 2.3 V 8 mA VCC= 2.7 V 12 mA VCC= 3 V . 24 mA Maximum input transition rise or fall rate

13、 (t/v) . 10 ns/V Operating free-air temperature range (TA) -40C to +85C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indica

14、ted under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3/ The value of

15、VCCis provided in the recommended operating conditions table. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permit

16、ted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04724 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 H

17、igh Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall

18、be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and wi

19、th items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physic

20、al dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The t

21、erminal connections shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS,

22、 OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04724 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max High level output voltage VOHIOH= -100 A 1.65 V to 3.6 V 25C, -40C to 85C All VCC 0.2 V IOH= -4 mA 1.65 V 1.2

23、IOH= -8 mA 2.3 V 1.7 IOH= -12 mA 2.7 V 2.2 3 V 2.4 IOH= -24 mA 3 V 2.2 Low level output voltage VOLIOL= 100 A 1.65 V to 3.6 V 0.2 V IOL= 4 mA 1.65 V 0.45 IOL= 8 mA 2.3 V 0.7 IOL= 12 mA 2.7 V 0.4 IOL= 24 mA 3 V 0.55 Input current IIVI= 0 V to 5.5 V 3.6 V 5 A Input/output power-off leakage current Iof

24、fVIor VO= 5.5 V 0 V 10 A 3-state output current IOZVO= 0 V to 5.5 V 3.6 V 10 A Quiescent supply current ICCVI= VCCor GND IO= 0 A 3.6 V 20 A 3.6 V VI 5.5 V 2/ IO= 0 A 20 Quiescent supply current delta ICCOne input at VCC 0.6 V, Other inputs at VCCor GND 2.7 V to 3.6 V 500 A Input capacitance CiVI= VC

25、Cor GND 3.3 V 25C 5.5 TYP pF Output capacitance CoVO= VCCor GND 6 TYP pF Power dissipation capacitance per buffer/driver CpdOutputs enabled f = 10 MHz 1.8 V 33 TYP pF 2.5 V 35 TYP 3.3 V 39 TYP Outputs disabled f = 10 MHz 1.8 V 2 TYP 2.5 V 3 TYP 3.3 V 4 TYP See footnotes at end of table. Provided by

26、IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04724 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions VCCTemperature, TADev

27、ice type Limits Unit Min Max Propagation delay time, A to Y tpdSee figure 5 1.8 V 0.15 V 25C, -40C to 85C All 1.5 6.6 ns 2.5 V 0.2 V 1 3.9 2.7 V 1 4.7 3.3 V 0.3 V 1.1 4.1 Propagation delay time, output enable, OEto Y ten1.8 V 0.15 V 1.5 7.5 ns 2.5 V 0.2 V 1 4.7 2.7 V 1 5.8 3.3 V 0.3 V 1 4.6 Propagat

28、ion delay time, output disable, OEto Y tdis1.8 V 0.15 V 1.5 10.3 ns 2.5 V 0.2 V 1 5.3 2.7 V 1 6.2 3.3 V 0.3 V 1.8 5.8 Output skew time tsk(o)3.3 V 0.3 V 1 ns 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified tempe

29、rature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ This applies in the disabled state only. Provide

30、d by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04724 REV A PAGE 7 Case X Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A

31、 - 1.20 - 0.047 E1 6.00 6.20 0.236 0.244 A1 0.05 0.15 0.002 0.006 e 0.50 TYP 0.020 TYP b 0.17 0.27 0.007 0.011 L 0.50 0.75 0.020 0.030 D 12.40 12.60 0.488 0.496 L1 0.25 TYP 0.010 TYP E 7.90 8.30 0.311 0.327 L2 0.15 NOM 0.006 NOM NOTES: 1. This drawing is subject to change without notice. 2. Falls wi

32、thin JEDEC MO-153. 3. All linear dimensions are shown in millimeters (inches). Inches equivalents are given for general information only. 4. Body dimensions do not include mold flash or protrusion not to exceed 0.15 millimeters (0.006 inches). FIGURE 1. Case outline. Provided by IHSNot for ResaleNo

33、reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04724 REV A PAGE 8 (each 4-bit buffer) Inputs Output Y OEA L L H L H X H L Z H = High L = Low X = Immaterial Z = High impedance state FIGURE 2. Tru

34、th table. FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04724 REV A PAGE 9 Device type 01 Case outline X Terminal number Terminal symbol

35、 Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 OE1Y1 1Y2 GND 1Y3 1Y4 VCC2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 VCC4Y1 4Y2 GND 4Y3 4Y4 4 OE25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 3 OE4A4 4A3 GND 4A2 4A1 VCC3A4 3A3 GND

36、 3A2 3A1 2A4 2A3 GND 2A2 2A1 VCC1A4 1A3 GND 1A2 1A1 2 OEFIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04724 REV A PAGE 10 NOTES:

37、1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. Al

38、l input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO= 50. 4. The outputs are measured one at a time with one input transition per measurement. 5. tPLHand tPHLare the same as tpd. 6. tPZLand tPZHare the same as ten. 7. tPLZand tPHZare the same as tdis. FIGURE

39、 5. Timing waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04724 REV A PAGE 11 4. VERIFICATION 4.1 Product assurance requirements. The

40、manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PR

41、EPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS

42、class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(

43、s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top-Side Marki

44、ng V62/04724-01XE 01295 CLVC16244AIDGGREP C16244AEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-