DLA DSCC-VID-V62 04725 REV A-2011 MICROCIRCUIT DIGITAL ADVANCED CMOS DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 11-08-22 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing RE

2、V PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED CMOS, DUAL POSITIVE-EDGE-

3、TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON YY-MM-DD 04-06-09 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04725 REV A PAGE 1 OF 10 AMSC N/A 5962-V070-11 Provided by IHSNot for ResaleNo reproduction or networking permitted withou

4、t license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04725 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance dual positive-edge-triggered D-type flip-flop with clear and preset, TTL compatib

5、le inputs microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering d

6、ocumentation: V62/04725 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74ACT74-EP Dual positive-edge-triggered D-type flip-flop with clear and preset, TTL compatible inputs 1.2.2 Case ou

7、tlines. The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 14 JEDEC MS-012 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material

8、A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04725 REV A PAGE 3 1.3 Ab

9、solute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to +7.0 V Input voltage range (VI) . -0.5 V to VCC+ 0.5 V 2/ Output voltage range (VO) . -0.5 V to VCC+ 0.5 V 2/ Input clamp current (IIK) (VIVCC) 20 mA Output clamp current (IOK) (VOVCC) 20 mA Continuous output current (IO) (VO= 0 to VC

10、C) 50 mA Continuous current through VCCor GND . 200 mA Package thermal impedance (JA) . 86C/W 3/ Storage temperature range (TSTG) . -65C to +150C 4/ 1.4 Recommended operating conditions. 5/ Supply voltage range (VCC) . 4.5 V to 5.5 V Minimum high level input voltage (VIH) 2 V Maximum low level input

11、 voltage (VIL) . 0.8 V Input voltage range (VI) . 0.0 V to VCCOutput voltage range (VO) . 0.0 V to VCCMaximum high level output current (IOH) . -24 mA Maximum low level output current (IOL) . 24 mA Maximum input transition rise or fall rate (t/v) . 8 ns/V Operating free-air temperature range (TA) -5

12、5C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.

13、 Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The package thermal impedance is calculated in accordance with JESD 51-7. 4/ Long-term h

14、igh-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitt

15、ed without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04725 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 Hi

16、gh Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall b

17、e permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and wit

18、h items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physica

19、l dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The te

20、rminal connections shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS,

21、OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04725 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max High level output voltage VOHIOH= -50 A 4.5 V 25C, -55C to 125C All 4.4 V 5.5 V 5.4 IOH= -24 mA 4.5 V 25C 3.86

22、-55C to 125C 3.7 5.5 V 25C 4.86 -55C to 125C 4.7 Low level output voltage VOLIOL= 50 A 4.5 V 25C, -55C to 125C 0.1 V 5.5 V 0.1 IOL= 24 mA 4.5 V 25C 0.36 -55C to 125C 0.5 5.5 V 25C 0.36 -55C to 125C 0.5 Input current IIVI= VCCor GND 5.5 V 25C 0.1 A -55C to 125C 1 Quiescent supply current ICCVI= VCCor

23、 GND IO= 0 A 5.5 V 25C 2 A -55C to 125C 40 Quiescent supply current delta ICC2/ One input at 3.4 V, Other inputs at VCCor GND 5.5 V 25C, -55C to 125C 1.6 mA Input capacitance CIVI= VCCor GND 5 V 25C 3 TYP pF Power dissipation capacitance CpdCL= 50 pF f = 1 MHz 5 V 25C 45 TYP pF See footnotes at end

24、of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04725 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions

25、 VCCTemperature, TADevice type Limits Unit Min Max Clock frequency fclock4.5 V and 5.5 V 25C All 145 MHz -55C to 125C 85 Pulse duration twPREor CLRlow See figure 5 4.5 V and 5.5 V 25C 5 ns -55C to 125C 7 CLK See figure 5 4.5 V and 5.5 V 25C 5 -55C to 125C 7 Setup time, data before CLK tsuData See fi

26、gure 5 4.5 V and 5.5 V 25C 3 ns -55C to 125C 4 PREor CLRinactive See figure 5 4.5 V and 5.5 V 25C 0 -55C to 125C 0.5 Hold time, data after CLK thSee figure 5 4.5 V and 5.5 V 25C 1 ns -55C to 125C 1 Maximum frequency fmax4.5 V and 5.5 V 25C 145 MHz -55C to 125C 85 Propagation delay time, PREor CLRto

27、Q or QtPLHSee figure 5 4.5 V and 5.5 V 25C 1 9.5 ns -55C to 125C 1 11.5 tPHL4.5 V and 5.5 V 25C 1 10 -55C to 125C 1 12.5 Propagation delay time, CLK to Q or QtPLH4.5 V and 5.5 V 25C 1 11 ns -55C to 125C 1 14 tPHL4.5 V and 5.5 V 25C 1 10 -55C to 125C 1 12 1/ Testing and other quality control techniqu

28、es are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance

29、is assured by characterization and/or design. 2/ This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER,

30、COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04725 REV A PAGE 7 Case X Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A - 1.75 - .069 E 3.81 4.00 .150 .157 A1 0.10 0.25 .004 .010 E1 5.80 6.20 .228 .244 b 0.35 0.51 .014 .020 e 1.27 NO

31、M .050 NOM c 0.20 NOM .008 NOM L 0.40 1.12 .016 .044 D 8.55 8.75 .337 .344 NOTES: 1. This drawing is subject to change without notice. 2. Body dimensions do not include mold flash or protrusion not to exceed 0.006 inches (0.15 mm). 3. Falls within JEDEC MS-012. 4. All linear dimensions are shown in

32、inches (millimeters). Metric equivalents are given for general information only. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04725 REV

33、A PAGE 8 (each flip-flop) Inputs Outputs PRECLRCLK D Q Q L H L H H H H L L H H H X X X L X X X H L X H L H* H L Q0L H H* L H Q0H = High level X = Immaterial L = Low level = Rising edge of CLK * = This configuration is nonstable; that is, it does not persist when either PREor CLRreturns to its inacti

34、ve (high) level. Q0= Level of Q before the indicated steady-state input conditions were established. Q0= Complement of Q0or level of Q before the indicated steady-state input conditions were established. FIGURE 2. Truth table. FIGURE 3. Logic diagram. Device type 01 Case outline X Terminal number Te

35、rminal symbol Terminal number Terminal symbol 1 1CLR 8 2Q 2 1D 9 2Q 3 1CLK 10 2PRE 4 1PRE 11 2CLK 5 1Q 12 2D 6 1Q 13 2CLR 7 GND 14 VCCFIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLU

36、MBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04725 REV A PAGE 9 NOTES: 1. CLincludes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO= 50, tr 2.5 ns, tf 2.5 ns. 3. The outputs are measured one at a time with one input

37、 transition per measurement. 4. For tPLH/tPHLtests, S1 = Open FIGURE 5. Timing waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04725 RE

38、V A PAGE 10 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packagi

39、ng, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devic

40、es are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This dra

41、wing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control numbe

42、r 1/ Device manufacturer CAGE code Vendor part number Top-Side Marking V62/04725-01XE 01295 SN74ACT74MDREP SACT74MEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-