DLA DSCC-VID-V62 04736 REV A-2011 MICROCIRCUIT DIGITAL SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 11-09-16 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing RE

2、V PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, SINGLE BUS BUFFER GATE WITH 3-STATE O

3、UTPUTS, MONOLITHIC SILICON YY MM DD 04-07-07 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04736 REV A PAGE 1 OF 11 AMSC N/A 5962-V077-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS,

4、OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04736 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance single bus buffer gate with 3-state output microcircuit, with an operating temperature range of -40C to +85C. 1.2 Vendor Item Drawing Administrati

5、ve Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04736 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See

6、1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVC1G126-EP Single bus buffer gate with 3-state outputs. 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 5 JEDEC MO-203 Plastic small outline package

7、1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range, (VC

8、C) . -0.5 V to +6.5 V Input voltage range, (VI) . -0.5 V to +6.5 V 2/ Voltage range applied to any output in the high impedance or power-off stage, (VO) -0.5 V to +6.5 V 2/ Voltage range applied to any output in the high or slow state, (VO) . -0.5 V to VCC+ 0.5 V 2/ 3/ Input clamp current, (IIK) (VI

9、 0) -50 mA Output clamp current, (IOK) (VO 0) . -50 mA Continuous output current, (IO) . 50 mA Continuous current through VCCor GND 100 mA Package thermal impedance (JA) 252C/W 4/ Storage temperature range, (TSTG) -65C to +150C 1/ Stresses beyond those listed under “absolute maximum rating” may caus

10、e permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect devic

11、e reliability. 2/ The input and output negative voltage ratings may exceeded if the input and output current ratings are observed. 3/ The value of VCCis provided in the recommended operating conditions table. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. Provided by IH

12、SNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04736 REV A PAGE 3 1.4 Recommended operating conditions. 5/ Supply voltage, (VCC): Operating +1.65 V to +5.5 V Minimum data reten

13、tion only . +1.5 V Minimum high level input voltage, (VIH): VCC= 1.65 V to 1.95 V +0.65 x VCCVCC= 2.3 V to 2.7 V +1.7 V VCC= 3.0 to 3.6 V . +2.0 V VCC= 4.5 V to 5.5 V +0.7 x VCCMaximum low level input voltage, (VIL): VCC= 1.65 V to 1.95 V +0.35 x VCCVCC= 2.3 V to 2.7 V +0.7 V VCC= 3.0 to 3.6 V . +0.

14、8 V VCC= 4.5 V to 5.5 V +0.3 x VCCInput voltage, (VI) 0.0 V to +5.5 V Output voltage, (VO) 0.0 V to VCCMaximum high level output current, (IOH): VCC= 1.65 V . -4 mA VCC= 2.3 V . -8 mA VCC= 3.0 V . -16 mA VCC= 3.0 V . -24 mA VCC= 4.5 V . -32 mA Maximum low level output current, (IOH): VCC= 1.65 V . 4

15、 mA VCC= 2.3 V . 8 mA VCC= 3.0 V . 16 mA VCC= 3.0 V . 24 mA VCC= 4.5 V . 32 mA Maximum Input transition rise or fall rate (t/v): VCC= 1.8 V 0.15 V, 2.5 V 0.2 V 20 ns/V VCC= 3.3 V 0.3 V . 10 ns/V VCC= 5 V 0.5 V 5 ns/V Operating free air temperature, (TA) -40C to +85C 2. APPLICABLE DOCUMENTS JEDEC SOL

16、ID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 5/ All un

17、used inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04736 REV A PAGE 4 3. REQUIR

18、EMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the

19、manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The

20、design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be

21、 as shown in figure 3. 3.5.4 Function table. The function table shall be as shown in figure 4. 3.5.5 Load circuit and voltage waveforms. The load circuit and timing waveforms shall be as specified in figure 5 and 6. Provided by IHSNot for ResaleNo reproduction or networking permitted without license

22、 from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04736 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions -40C TA +85C unless otherwise specified VCCLimits Unit Min Max High level output voltage VOHIOH= -100 A 1

23、.65 V to 5.5 V VCC 0.1 V IOH= -4 mA 1.65 V 1.2 IOH= -8 mA 2.3 V 1.9 IOH= -16 mA 3.0 V 2.4 IOH= -24 mA 2.3 IOH= -32 mA 4.5 V 3.8 Low level output voltage VOLIOL= 100 A 1.65 V to 5.5 V 0.1 IOL= 4 mA 1.65 V 0.45 IOL= 8 mA 2.3 V 0.3 IOL= 16 mA 3.0 V 0.4 IOL= 24 mA 0.55 IOL= 32 mA 4.5 V 0.55 Input curren

24、t A or B inputs IIVI= 5.5 V or GND 0 to 5.5 V 5 A Input/output power off leakage current IoffVIor VO= 5.5 V 0 10 A High impedance state output current IOZVO= 0 to 5.5 V 3.6 V 10 A Quiescent supply current ICCVI= 5.5 V or GND, IO= 0 1.65 V to 5.5 V 10 A Quiescent supply current delta ICCOne input at

25、VCC 0.6 V, Other inputs at VCCor GND 3 V to 5.5 V 500 A Input capacitance CiVI= VCCor GND, VCC = 3.3 V, TA= 25C 3.3 V 4 TYP pF Propagation delay time from input A to output Y tpdCL= 15 pF See figure 5 1.8 V 0.15 V 1.7 6.9 ns 2.5 V 0.2 V 0.6 4.6 3.3 V 0.3 V 0.6 3.7 5 V 0.5 V 0.5 3.4 Propagation delay

26、 time from input A to output Y tpdCL= 30 pF or 50 pF See figure 6 1.8 V 0.15 V 2.6 8 2.5 V 0.2 V 1.1 5.5 3.3 V 0.3 V 1 4.5 5 V 0.5 V 1 4 See footnote at end of the table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS

27、 COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04736 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -40C TA +85C unless otherwise specified VCC2/ Unit Min Max Enable time from input OE to output Y tenCL= 30 pF or 50 pF See figure 6 1.8 V 0.1

28、5 V 2.8 9.4 ns 2.5 V 0.2 V 1.3 6.6 3.3 V 0.3 V 1.2 5.3 5 V 0.5 V 1 5 Disable time from input OE to output Y tdisCL= 30 pF or 50 pF See figure 6 1.8 V 0.15 V 1.6 9.8 2.5 V 0.2 V 1 5.5 3.3 V 0.3 V 1 5.5 5 V 0.5 V 1 4.2 Power dissipation capacitance Cpdf = 10 MHz Outputs enabled 1.8 V 19 TYP pF 2.5 V 1

29、9 TYP 3.3 V 19 TYP 5.0 V 21 TYP Outputs disabled 1.8 V 2 TYP 2.5 V 2 TYP 3.3 V 3 TYP 5.0 V 4 TYP 1. Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across th

30、e full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY

31、 CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04736 REV A PAGE 7 Case X Dimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max A .031 .043 0.80 1.10 E .043 .055 1.10 1.40 A1 .000 .004 0.00 0.10 E1 .070 .094 1.80 2.40 b .006 .012 0.15

32、 0.30 e .025 BSC 0.65 BSC c .005 NOM 0.13 NOM L .010 .018 0.26 0.46 D .072 .084 1.85 2.15 L1 .006 TYP 0.15 TYP Notes: 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. 4. Fall within JEDEC MO-

33、203. FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04736 REV A PAGE 8 Case X Pin No. Signal name 1 OE 2 A 3 GND 4 Y 5 VCCFIGURE 2. Termi

34、nal connections. FIGURE 3. Logic diagram. Inputs Output Y OE A H H H H L L L X Z FIGURE 4. Function Table Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04736 REV

35、 A PAGE 9 Notes: 1. CLincludes probe and test fixture capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled

36、by the output control. 3. All input pulses are supplied by generators having following characteristics: PRR 10 MHz, ZO= 50 . 4. The outputs are measured one at a time with one transition per measurement. 5. tPLZand tPHZare the same tdis. 6. tPZLand tPZHare the same ten. 7. tPLHand tPHLare the same t

37、pd. 8. All parameters and waveforms are not applicable to all devices. FIGURE 5. Load circuit and voltage waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V6

38、2/04736 REV A PAGE 10 Notes: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabl

39、ed by the output control. 3. All input pulses are supplied by generators having following characteristics: PRR 10 MHz, ZO= 50 . 4. The outputs are measured one at a time with one transition per measurement. 5. tPLZand tPHZare the same tdis. 6. tPZLand tPZHare the same ten. 7. tPLHand tPHLare the sam

40、e tpd. 8. All parameters and waveforms are not applicable to all devices. FIGURE 6. Load circuit and voltage waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO.

41、 V62/04736 REV A PAGE 11 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classifica

42、tion, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.

43、1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without not

44、ice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative

45、control number 1/ Device manufacturer CAGE code Vendor part number Top side marking 2/ V62/04736-01XE 01295 CLVC1G126IDCKREP CN_ 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ DCK: The actual top side marking has

46、one additional character that designates the assembly/test site. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-