DLA DSCC-VID-V62 04739 REV A-2011 MICROCIRCUIT DIGITAL HIGH SPEED CMOS LOGIC OCTAL D-TYPE FLIP FLOP 3-STATE POSITIVE EDGE TRIGGERED MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 11-09-16 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing RE

2、V PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Phu H Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Phu H Nguyen TITLE MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS LOGIC OCTAL D-TYPE FLIP FLOP

3、 3-STATE, POSITIVE EDGE TRIGGERED, MONOLITHIC SILICON YY MM DD 04-07-08 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04739 REV A PAGE 1 OF 10 AMSC N/A 5962-V080-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY

4、CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04739 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance high speed CMOS logic octal D-type flip flop 3-state, positive edge triggered microcircuit, with an operating temperatu

5、re range of -40C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04739 - 01 X E Drawing Device typ

6、e Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 CD74HCT574-EP High speed CMOS logic octal D-type flip -flop. 3-state, positive edge triggered 1.2.2 Case outline(s). The case outlines are as specified herein. Outline

7、letter Number of pins JEDEC PUB 95 Package style X 20 JEDEC MO-013 Plastic small outline package Y 20 JEDEC MO-153 Plastic small outline package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A H

8、ot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04739 REV A PAGE 3 1.3 Absol

9、ute maximum ratings. 1/ Supply voltage range, (VCC) . -0.5 V to +7.0 V 2/ Input clamp current, (IIK) (VIVCC+ 0.5 V) 20 mA Output clamp current, (IOK) (VOVCC+ 0.5 V) 20 mA Drain current per output, (IO) (VO -0.5 V or VO-0.5 V or VO VCC+ 0.5 V) 25 mA Continuous current through VCCor GND, (ICC) . 50 mA

10、 Package thermal impedance (JA): 3/ Case X 58C/W Case Y 69C/W Maximum junction temperature, (TJ) 150C Lead temperature (during soldering): At distance 1/16 1/32 inch (1.59 0.79 mm) from case for 10 s max 300C Storage temperature range, (TSTG) -65C to +150C 4/ 1.4 Recommended operating conditions. 4/

11、 Supply voltage, (VCC) . +4.5 V to +5.5 V Minimum high level input voltage, (VIH) (VCC= 4.5 V to 5.5 V) . +2.0 V Maximum low level input voltage, (VIL) (VCC= 4.5 V to 5.5 V) . +0.8 V Input voltage, (VI) . 0.0 V to VCC Output voltage, (VO) . 0.0 V to VCC Input transition (rise and fall) time, (tt): V

12、CC= 2 V . 0 ns to 1000 ns VCC= 4.5 V 0 ns to 500 ns VCC= 6 V . 0 ns to 400 ns Operating free air temperature, (TA) -40C to +125C 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents

13、 are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows

14、: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other cond

15、itions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ All voltage referenced to GND unless otherwise specified. 3/ The package thermal impedance is calculated in acco

16、rdance with JESD 51-7. 4/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO.

17、V62/04739 REV A PAGE 4 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified

18、in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal con

19、nections shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Function table. The function table shall be as shown in figure 4. 3.5.5 Load circuit and voltage waveforms. The load circuit and timing waveforms shall be as specified in figure 5. Pro

20、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04739 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions unless otherwise specifi

21、ed IO(mA) VCCTA= 25C -40C TA +125C Unit Min Max Min Max High level output voltage VOHVI= VIHor VILCMOS loads -0.02 4.5 V 4.4 4.4 V TTL loads -6 4.5 V 3.98 3.7 Low level output voltage VOLVI= VIHor VILCMOS loads 0.02 4.5 V 0.1 0.1 TTL loads 6 4.5 V 0.26 0.4 Input current IIVI= VCCor GND 0 5.5 V 0.1 1

22、 A High impedance state output current IOZVI= VIHor VIL, VO= VCCor GND 6 V 0.5 10 Quiescent supply current ICCVI= VCCor GND 0 5.5 V 8 160 Quiescent supply current delta ICCVI= VCC 2.1 V , 2/ 4.5 V to 5.5 V 360 490 Input capacitance CINCL= 50 pF 10 10 pF Output capacitance COUT3-statwe 20 20 Maximum

23、clock frequency fmax4.5 V 30 20 MHz Clock pulse duration tw4.5 V 16 24 ns Setup time, data before clock tsu 4.5 V 12 18 Hold time, data after clock th 4.5 V 5 5 Propagation delay time from input CP to output Q tpdCL= 50 pF 4.5 V 33 50 CL= 15 pF 5 V 15 Disable time from input OE to output Q tdisCL= 5

24、0 pF 4.5 V 28 42 CL= 15 pF 5 V 11 Enable time from input OE to output Q tenCL= 50 pF 4.5 V 30 45 CL= 15 pF 5 V 12 Transition time to output Q ttCL= 50 pF 4.5 V 12 18 Maximum frequency from input CP fmaxCL= 15 pF 5 V 60 MHz Power dissipation capacitance Cpd3/ Input tr, tf= 6 ns 5 V 47 pF 1. Testing a

25、nd other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific paramet

26、ric testing, product performance is assured by characterization and/or design. 2. For dual supply systems, theoretical worst case (VI= 2.4 V, VCC= 5.5 V) specification is 1.8 mA HCT input loading Type Input Unit Loads Unit loads is ICC limit specified in electrical characteristics table e.g 360 A ma

27、x at 25C D0-D7 0.4 CP 0.75 OE 0.6 3. Cpd is used to determine the dynamic power consumption (PD), per package. PD= (CPDx VCC2x fI) + (CLx VCC2x fO) where: fI= input frequency fO= output frequency CL= output load capacitance VCC= supply voltage Provided by IHSNot for ResaleNo reproduction or networki

28、ng permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04739 REV A PAGE 6 Case X Dimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max A .104 2.65 E .291 .299 7.39 7.59 A1 .004 .012 0.1

29、0 0.30 E1 .400 .419 10.15 10.65 b .014 .020 0.35 0.51 e .050 BSC 1.27 BSC c .010 NOM 0.25 NOM L .016 .050 0.40 1.27 D .500 .510 12.70 12.95 NOTES: 1. All linear dimensions are in inches (millimeters). 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash o

30、r protrusion not to exceed 0.006 (0.15). 4. Fall within JEDEC MO-013. FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04739 REV A PAGE 7 C

31、ase Y Dimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max A .047 1.20 E .168 .176 4.30 4.50 A1 .000 .006 0.05 0.15 E1 .242 .258 6.20 6.60 b .007 .012 0.19 0.30 e .025 BSC 0.65 BSC c .006 NOM 0.15 NOM L .020 .029 0.50 0.75 D .250 .258 6.40 6.60 NOTES: 5. All

32、 linear dimensions are in millimeters. 6. This drawing is subject to change without notice. 7. Body dimensions do not include mold flash or protrusion not to exceed 0.15. 8. Fall within JEDEC MO-153. FIGURE 1. Case outlines - Continued. Provided by IHSNot for ResaleNo reproduction or networking perm

33、itted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04739 REV A PAGE 8 Pin No. Signal name Pin No. Signal name 1 OE 11 CP 2 D0 12 Q7 3 D1 13 Q6 4 D2 14 Q5 5 D3 15 Q4 6 D4 16 Q3 7 D5 17 Q2 8 D6 18 Q1 9 D7 19 Q0 10 GND 20 VCCFIGURE

34、2. Terminal connections. FIGURE 3. Logic diagram. Inputs Output Q OE CP D L H H L L L L L X Q0H X X Z H = High voltage level (steady state) = Transition from low to high level L = Low voltage level (steady state) Q0= Level before indicated steady state conditions were established. X = Dont care Z =

35、High impedance state FIGURE 4. Function Table Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04739 REV A PAGE 9 NOTES: 1. CLincludes probe and test fixture capaci

36、tance. 2. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. 3. All input pulses are supplied by g

37、enerators having following characteristics: PRR 10 MHz, ZO= 50 , tr 6 ns, tf 6 ns. 4. The outputs are measured one at a time with one transition per measurement. 5. All parameters and waveforms are not applicable to all devices. 6. tPLHand tPHLare the same tpd. 7. tPLZand tPHZare the same tdis. 8. t

38、PZHand tPZLare the same ten. FIGURE 5. Load circuit and voltage waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04739 REV A PAGE 10 4. VERIFICATION 4.1

39、Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sen

40、sitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge s

41、ensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes

42、 are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE co

43、de Vendor part number Top side marking V62/04739-01XE 01295 CD74HCT574QM96EP HCT574EP V62/04739-01YE 01295 CD74HCT574QPWREP HCT574EP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-