DLA DSCC-VID-V62 04752 REV B-2011 MICROCIRCUIT DIGITAL-LINEAR PHASE SHIFT RESONANT CONTROLLER MONOLITHIC SILICON.pdf

1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Correct lead finish on last page. - CFS 05-12-07 Thomas M. Hess B Make change to VCpin description as specified under figure 2. Update boilerplate paragraphs to current requirements. - ro 11-09-07 Charles F. Saffle CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS

2、CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV B B B B B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER

3、COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY TOM HESS TITLE MICROCIRCUIT, DIGITAL-LINEAR, PHASE SHIFT RESONANT CONTROLLER, MONOLITHIC SILICON 04-11-19 APPROVED BY RAYMOND MONNIN SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04752 REV B PAGE 1 OF 16 AMSC N/A 5962-V066-11

4、 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04752 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance phase

5、 shift resonant controller microcircuit, with an operating temperature range of -25C to +110C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on

6、the engineering documentation: V62/04752 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 UC2875-EP Phase shift resonant controller 1.2.2 Case outline(s). The case outline(s) are as specifie

7、d herein. Outline letter Number of pins JEDEC PUB 95 Package style X 28 MS-013 Plastic small outline1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD Pa

8、lladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04752 REV B PAGE 3 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage ( VC,VI

9、N) . 20 V Output current (sink or source), IODC . 0.50 A Pulse (0.5 s) . 3 A Analog I/O voltage -0.3 V to 5.3 V Power dissipation (PD) . 1.488 W Operating junction temperature range (TJ) -55C to +150C Storage temperature range (TSTG) -65C to +150C Lead temperature soldering 1.6 mm (1/16 inch) from c

10、ase for 10 seconds . +300C Thermal resistance, junction to ambient (JC): X package 20.6C/W (high K board) Thermal resistance, junction to ambient (JA): X package 45.5C/W (high K board) 1.4 Recommended operating conditions. 3/ Supply voltage range ( VC,VIN) . 12 V Operating free-air temperature range

11、 ( TA) . -25C to +110C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is n

12、ot implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Unless otherwise indicated, voltages are reference to ground and currents are positive into and negative out of the specified terminals. 3/ Use of this product beyond the manufacturers de

13、sign rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, C

14、OLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04752 REV B PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the JEDEC Office, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201

15、-2107 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit contai

16、ner. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 D

17、esign, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.

18、3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Timing waveforms. The timing waveforms shall be as shown in figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE I

19、DENT NO. 16236 DWG NO. V62/04752 REV B PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Max Undervoltage lockout (UVLO) section. Start threshold -25C to +110C 01 11.75 V UVLO hysteresis -25C to +110C 01 0.5 2 V Supply curr

20、ent section. Supply current, IINstartup VIN= 8 V, VC= 20 V, RSLOPEopen, IDELAY= 0 -25C to +110C 01 600 A Supply current, ICstartup VIN= 8 V, VC= 20 V, RSLOPEopen, IDELAY= 0 -25C to +110C 01 100 A Supply current, IIN-25C to +110C 01 44 mA Supply current, IC-25C to +110C 01 30 mA Voltage reference sec

21、tion. Output voltage TJ= +25C 01 4.92 5.08 V Line regulation voltage VLNVIN= 11 V to 20 V -25C to +110C 01 10 mV Load regulation voltage VLDIVREF= -10 mA -25C to +110C 01 20 mV Total variation Line, load, temperature -25C to +110C 01 4.9 5.1 V Noise voltage 10 Hz to 10 kHz -25C to +110C 01 50 typica

22、l Vrms Long term stability 1000 hours TJ= +125C 01 2.5 typical mV Short circuit current VREF= 0 V TJ= +25C 01 60 typical mA Error Amplifier section. Offset voltage -25C to +110C 01 15 mV Input bias current -25C to +110C 01 3 A Open loop voltage gain AVOLVE/AOUT= 1 V to 4 V -25C to +110C 01 60 dB Com

23、mon mode rejection ratio CMRR VCM= 1.5 V to 5.5 V -25C to +110C 01 75 dB See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04752 REV B

24、 PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Max Error Amplifier section continued. Power supply rejection ratio PSRR VIN= 11 V to 20 V -25C to +110C 01 85 dB Output sink current VE/AOUT= 1 V -25C to +110C 0

25、1 1 mA Output source current VE/AOUT= 4 V -25C to +110C 01 -0.5 mA High level output voltage VOHIE/AOUT= -0.5 mA -25C to +110C 01 4 5 V Low level output voltage VOLIE/AOUT= 1 mA -25C to +110C 01 0 1 V Unity gain bandwidth UGBW -25C to +110C 01 7 MHz Slew rate -25C to +110C 01 6 V/sec Pulse Width Mod

26、ulator (PWM) comparator section. Ramp offset voltage 3/ TJ= +25C 01 1.3 typical V Zero phase shift voltage 4/ -25C to +110C 01 0.55 V PWM phase shift 5/ VE/AOUT (Ramp peak + Ramp offset) -25C to +110C 01 98 102 % VE/AOUT Zero phase shift voltage 0 2 Output skew 5/ VE/AOUT 1 V -25C to +110C 01 20 ns

27、Ramp to output delay 6/ -25C to +110C 01 125 ns Oscillator section. Initial accuracy TJ= +25C 01 0.85 1.15 MHz Voltage stability VIN= 11 V to 20 V -25C to +110C 01 2 % Total variation Line, temperature -25C to +110C 01 0.80 1.20 MHz See footnotes at end of table. Provided by IHSNot for ResaleNo repr

28、oduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04752 REV B PAGE 7 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Ma

29、x Oscillator section continued. Sync pin threshold TJ= +25C 01 3.8 typical V Clock out peak TJ= +25C 01 4.3 typical V Clock out low TJ= +25C 01 3.3 typical V Clock out pulse width RCLOCKSYNC= 3.9 k -25C to +110C 01 100 ns Maximum frequency RFREQSET= 5 k -25C to +110C 01 2 MHz Ramp generator/slope co

30、mpensation section. Minimum ramp current ISLOPE= 10 A, VFREQSET= VREF-25C to +110C 01 -14 A Maximum ramp current ISLOPE= 1 mA, VFREQSET= VREF-25C to +110C 01 -0.8 mA Ramp valley -25C to +110C 01 0 typical V Ramp peak clamping level RFREQSET= 100 k -25C to +110C 01 4.1 V Current limit section. Input

31、bias current IIBVCS+= 3 V -25C to +110C 01 5 A Threshold voltage -25C to +110C 01 2.4 2.6 V Delay to output -25C to +110C 01 150 ns Soft start/reset delay section. Charge current VSOFTSTART= 0.5 V -25C to +110C 01 -20 -3 A Discharge current VSOFTSTART= 1 V -25C to +110C 01 120 A Restart threshold -2

32、5C to +110C 01 4.3 V Discharge level -25C to +110C 01 300 typical mV See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04752 REV B PAG

33、E 8 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Max Output drivers section. Output low level IOUT= 50 mA -25C to +110C 01 0.4 V IOUT= 500 mA 2.6 Output high level IOUT= -50 mA -25C to +110C 01 2.5 V IOUT= -500 mA 2

34、.6 Delay set section. Delay set voltage IDELAY= -500 A -25C to +110C 01 2.3 2.6 V Delay time IDELAY= -250 A 7/ 8/ -25C to +110C 01 150 600 ns 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Pr

35、oduct may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Unless otherwise specified, VC= VIN= 12 V, RFREQSET= 12 k, CFREQ

36、SET= 330 pF, RSLOPE= 12 k, CRAMP= 200 pF, CDELAYSET A-B= CDELAYSET C-D= 0.01 F, IDELAYSET A-B= IDELAYSET C-D= -500 A, and TA= TJ. 3/ Ramp offset voltage has a temperature coefficient of about 0.4 mV/C. 4/ Zero phase shift voltage has a temperature coefficient of about 0.2 mV/C. 5/ Phase shift percen

37、tage (0% = 0, 100% = 180) is defined as = 200/T %, where is the phase shift, and and T are defined in figure 4. At 0% phase shift, is the output skew. 6/ Ramp delay to output time is defined in NO TAG. 7/ Delay time is defined as delay = T (1/2 (duty cycle), where T is defined in figure 4. 8/ Delay

38、time can be programmed via resistors from the delay set pins to ground. Delay time (62.5 x 10-12) / IDELAYsec where IDELAY= delay set voltage / RDELAY. The recommended range for IDELAYis 25 A IDELAY 1 mA. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,

39、-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04752 REV B PAGE 9 Case X FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDE

40、NT NO. 16236 DWG NO. V62/04752 REV B PAGE 10 Case X Symbol Dimensions Inches Millimeters Min Max Min Max A - 0.104 - 2.65 A1 0.004 0.012 0.10 0.30 b 0.012 0.020 0.31 0.51 c 0.008 0.013 0.20 0.33 D 0.697 0.713 17.70 18.10 E 0.291 0.299 7.40 7.60 E1 0.393 0.419 9.97 10.63 e 0.050 BSC 1.27 BSC L 0.016

41、0.050 0.40 1.27 n 28 28NOTES: 1. This drawing is subject to change without notice. 2. Falls within JEDEC MS-013 variation AE. 3. All linear dimensions are shown in inches (millimeters). Millimeter equivalents are given for general information only. 4. Body dimensions do not include mold protrusion n

42、ot to exceed 0.006 inch (0.15 millimeters). FIGURE 1. Case outline - continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04752 REV B PAGE 11 Device type 01

43、Case outline X Terminal number Terminal symbol 1 VREF2 E/AOUT3 EA- 4 EA+ 5 CS+ 6 SOFTSTART 7 GND 8 GND 9 GND 10 DELAYSET C-D 11 NC12 OUTD 13 OUTC14 VC15 VIN16 PWRGND 17 OUTB 18 OUTA19 NC 20 GND 21 GND 22 GND 23 DELAYSET A-B 24 FREQSET 25 CLOCKSYNC 26 SLOPE 27 RAMP 28 GND FIGURE 2. Terminal connectio

44、ns. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04752 REV B PAGE 12 Pin DescriptionCLOCKSYNC Bi-directional clock and synchronization pin. Used as an output, t

45、his pin provides a clock signal. As an input, this pin provides a synchronization point. In its simplest useage, multiple devices, each with their own local oscillator frequency, may be connected together by the CLOCKSYNC pin and will synchronize on the fastest oscillator. This pin may also used to

46、synchronize the device to an external clock, provided the external signal is of higher frequency than the local oscillator. A resistor load may be needed on this pin to minimize the clock pulse width. E/AOUT Error amplifier output. This is the gain stage for overall feedback control. Error amplifier

47、 output voltage levels below 1 volt will force 0 phase shift. Since the error amplifier has a relatively low current drive capability, the output may be overridden by driving with a sufficiently low impedance source. CS+ Current sense. The non-inverting input to the current fault comparator whose reference is set internally to a fixed 2.5 V (separate from VREF). When the voltage at this pin exceeds 2.5 V the current fault latch is set,