DLA DSCC-VID-V62 04757 REV A-2011 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 11-09-16 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing RE

2、V PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED BIPOLAR CMOS, 1

3、LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS, MONOLITHIC SILICON YY-MM-DD 04-11-22 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04757 REV A PAGE 1 OF 12 AMSC N/A 5962-V081-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-

4、DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04757 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 1-line to 10-line clock driver with 3-state outputs microcircuit, with an operating temperature range

5、of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04757 - 01 X E Drawing Device type Case ou

6、tline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 CDC2351-EP 1-line to 10-line clock driver with 3-state outputs 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Pac

7、kage style X 24 JEDEC MO-150 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium 1.3 Absolute ma

8、ximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 4.6 V Input voltage range (VI) . -0.5 V to 7 V 2/ Voltage range applied to any output in the high state or power-off state (VO) -0.5 V to 3.6 V 2/ Current into any output in the low state (IO) . 24 mA Input clamp current (IIK) (VI 0) -18 mA Ou

9、tput clamp current (IOK) (VO 0) . -50 mA Maximum power dissipation at TA= 55C (PD) (in still air) 0.65 W 3/ Storage temperature range (TSTG) . -65C to +150C 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and f

10、unctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output negative-voltage ratings may be

11、 exceeded if the input and output clamp-current ratings are observed. 3/ The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DE

12、FENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04757 REV A PAGE 3 1.4 Recommended operating conditions. 4/ Supply voltage range (VCC) . 3 V to 3.6 V Minimum high-level input voltage (VIH) 2 V Maximum low-level input voltage (VIL) . 0.8 V Input voltage range (VI)

13、 . 0 V to 5.5 V Maximum high-level output current (IOH) . -12 mA Maximum low-level output current (IOL) . 12 mA Maximum input clock frequency (fclock) 100 MHz Operating free-air temperature range (TA) -55C to +125C 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95

14、 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and l

15、egibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if

16、 applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 4/ Unused pins (input or I/O) must be held high or low. Provided by IHSNot for ResaleNo reproduction or ne

17、tworking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04757 REV A PAGE 4 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 C

18、ase outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Function table. The function table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5

19、5 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04757 RE

20、V A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max Input clamp voltage VIKII= -18 mA 3 V 25C, -55C to 125C All -1.2 V High level output voltage VOHIOH= -12 mA 3 V 2 V Low level output voltage VOLIOL= 12 mA 3 V 0.8 V

21、 Input current IIVI= VCCor GND 3.6 V 1 A Output current IO2/ VO= 2.5 V 3.6 V -7 -70 mA Off-state output current IOZVO= 3 V or 0 V 3.6 V 10 A Quiescent supply current ICCOutputs high. VI= VCCor GND IO = 0 A 3.6 V 0.3 mA Outputs low. VI= VCCor GND IO = 0 A 15 Outputs disabled. VI= VCCor GND IO = 0 A 0

22、3 Input capacitance CiVI= VCCor GND f = 10 MHz 3.3 V 25C 4 TYP pF Output capacitance CoVO= VCCor GND f = 10 MHz 6 TYP pF Propagation delay time, A to Y tPLHCL= 50 pF See figure 5. 3.3 V 25C 3.8 4.8 ns 3 V to 3.6 V -55C to 125C 1.1 11 tPHL3.3 V 25C 3.6 4.6 3 V to 3.6 V -55C to 125C 1 9.7 Propagation

23、 delay time, output enable, OEto Y tPZHCL= 50 pF See figure 5. 3.3 V 25C 2.4 6 ns 3 V to 3.6 V -55C to 125C 1 12 tPZL3.3 V 25C 2.4 6 3 V to 3.6 V -55C to 125C 1 11.1 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFEN

24、SE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04757 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max Propagation delay time, output disable, OE to Y tPHZCL= 50 pF

25、See figure 5. 3.3 V 25C All 2.2 6.3 ns 3 V to 3.6 V -55C to 125C 1 11.1 tPLZ3.3 V 25C 2.2 6.3 3 V to 3.6 V -55C to 125C 1 11.5 Output skew time, A to Y tsk(o)CL= 50 pF See figure 5. 3.3 V 25C 0.5 ns 3 V to 3.6 V -55C to 125C 2.5 Pulse skew time, A to Y tsk(p)CL= 50 pF See figure 5. 3.3 V 25C 0.8 ns

26、3 V to 3.6 V -55C to 125C 3 Process skew time, A to Y tsk(pr)CL= 50 pF See figure 5. 3.3 V 25C 1 ns Rise time, A to Y trCL= 50 pF See figure 5. 3 V to 3.6 V -55C to 125C 2.5 ns Fall time, A to Y tfCL= 50 pF See figure 5. 3 V to 3.6 V -55C to 125C 2.5 ns Average temperature coefficient of low-to-high

27、 propagation delay, A to Y tPLH(T) 3/ 4/ 3 V to 3.6 V 25C, -55C to 125C 85 ps/ 10C Average temperature coefficient of high-to-low propagation delay, A to Y tPHL(T) 3/ 4/ 3 V to 3.6 V 25C, -55C to 125C 50 ps/ 10C Average VCCcoefficient of low-to- high propagation delay, A to Y tPLH(VCC) 3/ 5/ 3 V to

28、3.6 V 25C, -55C to 125C -145 ps/ 100 mV Average VCCcoefficient of high-to- low propagation delay, A to Y tPHL(VCC) 3/ 5/ 3 V to 3.6 V 25C, -55C to 125C -100 ps/ 100 mV 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the speci

29、fied temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Not more than one output should be tes

30、ted at a time, and the duration of the test should not exceed one second. 3/ This data was extracted from characterization material and has not been tested at the factory. 4/ tPLH(T) and tPHL(T) are virtually independent of VCC. 5/ tPLH(VCC) and tPHL(VCC) are virtually independent of temperature. Pr

31、ovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04757 REV A PAGE 7 Case X Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min

32、Max A - 2.00 - .079 E 5.00 5.60 .197 .220 A1 0.05 - .002 - E1 7.40 8.20 .291 .323 b 0.22 0.38 .009 .015 e 0.65 BSC .026 BSC c 0.09 0.25 .004 .010 L 0.55 0.95 .022 .037 D 7.90 8.50 .311 .335 NOTES: 1. This drawing is subject to change without notice. 2. Falls within JEDEC MO-150. 3. All linear dimens

33、ions are shown in millimeters (inches). Inches equivalents are given for general information only. 4. Body dimensions do not include mold flash or protrusion not to exceed 0.15 millimeters (0.006 inches). FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted wi

34、thout license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04757 REV A PAGE 8 Inputs Outputs Yn A OE L H L H H H L L Z Z L H H = High voltage level L = Low voltage level Z = High impedance state FIGURE 2. Function table. FIGURE 3. Logic diagram.

35、 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04757 REV A PAGE 9 Device type 01 Case outline X Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14

36、15 16 17 18 19 20 21 22 23 24 GND Y10 VCCY9 OE A P0 P1 Y8 VCCY7 GND GND Y6 VCCY5 GND Y4 Y3 GND Y2 VCCY1 GND FIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDE

37、NT NO. 16236 DWG NO. V62/04757 REV A PAGE 10 NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is hi

38、gh except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO= 50 , tr 2.5 ns, tf 2.5 ns. 4. The outputs are measured one at a time with one transition per measurement. FIGURE 5. Timing waveforms and test circuit. P

39、rovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04757 REV A PAGE 11 NOTES: A. Output skew, tsk(o), is calculated as the greater of: - The difference between the fas

40、test and slowest of tPLHn(n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10). - The difference between the fastest and slowest of tPHLn(n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10). B. Pulse skew, tsk(p), is calculated as the greater of |tPLHn tPHLn| ( n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10). C. Process skew, tsk(pr), is calculat

41、ed as the greater of: - The difference between the fastest and slowest of tPLHn(n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) across multiple devices under identical operating conditions. - The difference between the fastest and slowest of tPHLn(n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) across multiple devices under

42、identical operating conditions. FIGURE 5. Timing waveforms and test circuit - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04757 REV A PAGE 12 4. VER

43、IFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling o

44、f moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostat

45、ic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modif

46、ied as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufa

47、cturer CAGE code Vendor part number Top-Side Marking V62/04757-01XE 01295 CDC2351MDBREP CK2351MEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-