DLA DSCC-VID-V62 04758 REV A-2011 MICROCIRCUIT DIGITAL ADVANCED CMOS HEX INVERTER WITH TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 11-09-19 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing RE

2、V PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A PAGE 1 2 3 4 5 6 7 8 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED CMOS, HEX INVERTER, WITH TTL COMPA

3、TIBLE INPUTS, MONOLITHIC SILICON YY-MM-DD 04-12-09 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04758 REV A PAGE 1 OF 8 AMSC N/A 5962-V084-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUM

4、BUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04758 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance hex inverter, with TTL compatible inputs microcircuit, with an operating temperature range of -40C to +85C. 1.2 Vendor Item Drawing Administr

5、ative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04758 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (S

6、ee 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74ACT04-EP Hex inverter, with TTL compatible inputs 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 14 JEDEC MS-012 Plastic small-outline 1.2.3 Lea

7、d finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5

8、V to 7 V Input voltage range (VI) . -0.5 V to VCC+ 0.5 V 2/ Output voltage range (VO) . -0.5 V to VCC+ 0.5 V 2/ Input clamp current (IIK) (VIVCC) 20 mA Output clamp current (IOK) (VOVCC) 20 mA Continuous output current (IO) (VO= 0 to VCC) 50 mA Continuous current through VCCor GND . 200 mA Package t

9、hermal impedance (JA) . 86C/W 3/ Storage temperature range (TSTG) . -65C to +150C 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond t

10、hose indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The package therm

11、al impedance is calculated in accordance with JESD 51-7. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04758 REV A PAGE 3 1.4 Recommended operating conditions. 4

12、/ Supply voltage range (VCC) . 4.5 V to 5.5 V Minimum high-level input voltage (VIH) 2 V Maximum low-level input voltage (VIL) . 0.8 V Input voltage range (VI) . 0 V to VCCOutput voltage range (VO) . 0 V to VCCMaximum high-level output current (IOH) . -24 mA Maximum low-level output current (IOL) .

13、24 mA Maximum input transition rise or fall rate (t/v) . 8 ns/V Operating free-air temperature range (TA) -40C to +85C 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 High Effective Therma

14、l Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and l

15、egibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if

16、 applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as

17、 specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Function table. The function table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connec

18、tions shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as shown in figure 5. 4/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networkin

19、g permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04758 REV A PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max High level output voltage VO

20、HIOH= -50 A 4.5 V 25C, -40C to 85C 01 4.4 V 5.5 V 5.4 IOH= -24 mA 4.5 V 25C 3.86 -40C to 85C 3.76 5.5 V 25C 4.86 -40C to 85C 4.76 IOH= -75 mA 2/ 5.5 V -40C to 85C 3.85 Low level output voltage VOLIOL= 50 A 4.5 V 25C, -40C to 85C 0.1 V 5.5 V 0.1 IOL= 24 mA 4.5 V 25C 0.36 -40C to 85C 0.44 5.5 V 25C 0.

21、36 -40C to 85C 0.44 IOL= 75 mA 2/ 5.5 V -40C to 85C 1.65 Input current IIVI= VCCor GND 5.5 V 25C 0.1 A -40C to 85C 1 Quiescent supply current ICCVI= VCCor GND IO= 0 A 5.5 V 25C 2 A -40C to 85C 20 Quiescent supply current delta ICC3/ One input at 3.4 V, Other inputs at VCCor GND 5.5 V -40C to 85C 1.5

22、 mA Input capacitance CIVI= VCCor GND 5 V 25C 4.5 TYP pF Power dissipation capacitance CpdCL= 50 pF f = 1 MHz 5 V 25C 45 TYP pF Propagation delay time, A to Y tPLHCL= 50 pF See figure 5. 4.5 V and 5.5 V 25C 1 8.5 ns -40C to 85C 1 9 tPHL4.5 V and 5.5 V 25C 1 8 -40C to 85C 1 8.5 1/ Testing and other q

23、uality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testin

24、g, product performance is assured by characterization and/or design. 2/ Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms. 3/ This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0

25、 V or VCC. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04758 REV A PAGE 5 Case X Dimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max

26、 Min Max Min Max A - 0.069 - 1.75 E 0.150 0.157 3.80 4.00 A1 0.004 0.010 0.10 0.25 E1 0.228 0.244 5.80 6.20 b 0.012 0.020 0.31 0.51 e 0.050 BSC 1.27 BSC c 0.007 0.010 0.17 0.25 L 0.016 0.050 0.40 1.27 D 0.337 0.344 8.55 8.75 NOTES: 1. This drawing is subject to change without notice. 2. Falls within

27、 JEDEC MS-012. 3. All linear dimensions are shown in inches (millimeters). Millimeters equivalents are given for general information only. 4. Body dimensions do not include mold flash or protrusion not to exceed 0.006 inches (0.15 millimeters). FIGURE 1. Case outline. Provided by IHSNot for ResaleNo

28、 reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04758 REV A PAGE 6 (each inverter) Input A Output Y H L L H H = High voltage level L = Low voltage level FIGURE 2. Function table. FIGURE 3. Logic

29、 diagram. Device type 01 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 1A 8 4Y 2 1Y 9 4A 3 2A 10 5Y 4 2Y 11 5A 5 3A 12 6Y 6 3Y 13 6A 7 GND 14 VCCFIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fro

30、m IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04758 REV A PAGE 7 NOTES: 1. CLincludes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO= 50, tr 2.5 ns, tf 2.5 ns 3. The outp

31、uts are measured one at a time, with one input transition per measurement. FIGURE 5. Timing waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO.

32、 V62/04758 REV A PAGE 8 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classificat

33、ion, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1

34、 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without noti

35、ce. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative c

36、ontrol number 1/ Device manufacturer CAGE code Vendor part number Top-Side Marking V62/04758-01XE 01295 SN74ACT04IDREP SACT04IEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-