DLA DSCC-VID-V62 04762 REV A-2011 MICROCIRCUIT DIGITAL ADVANCED LOW-VOLTAGE CMOS OCTAL BUFFER DRIVER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 11-09-19 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing RE

2、V PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED LOW-VOLTAGE CMOS, OCTAL BUFFER

3、/DRIVER WITH 3-STATE OUTPUTS, MONOLITHIC SILICON YY-MM-DD 04-12-20 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04762 REV A PAGE 1 OF 9 AMSC N/A 5962-V088-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER

4、, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04762 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance octal buffer/driver with 3-state outputs microcircuit, with an operating temperature range of -40C to +85C. 1.2 Vendor Item D

5、rawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04762 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1

6、) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74ALVC244-EP Octal buffer/driver with 3-state outputs 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 20 JEDEC MO-153 Plastic small

7、-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Provided by IHSNot for ResaleNo reproduction or networkin

8、g permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04762 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 4.6 V Input voltage range (VI) . -0.5 V to 4.6 V 2/ Output voltage range (VO) . -

9、0.5 V to VCC+ 0.5 V 2/ 3/ Input clamp current (IIK) (VI 0) 50 mA Output clamp current (IOK) (VO 0) . 50 mA Continuous output current (IO) . 50 mA Continuous current through VCCor GND . 100 mA Package thermal impedance (JA) . 83C/W 4/ Storage temperature range (TSTG) . -65C to +150C 1.4 Recommended o

10、perating conditions. 5/ Supply voltage range (VCC) . 1.65 V to 3.6 V Minimum high-level input voltage (VIH): VCC= 1.65 V to 1.95 V . 0.65 x VCCVCC= 2.3 V to 2.7 V . 1.7 V VCC= 2.7 V to 3.6 V . 2 V Maximum low-level input voltage (VIL): VCC= 1.65 V to 1.95 V . 0.35 x VCCVCC= 2.3 V to 2.7 V . 0.7 V VC

11、C= 2.7 V to 3.6 V . 0.8 V Input voltage range (VI) . 0 V to 3.6 V Output voltage range (VO) . 0 V to VCCMaximum high-level output current (IOH): VCC= 1.65 V -4 mA VCC= 2.3 V -12 mA VCC= 2.7 V -12 mA VCC= 3 V . -24 mA Maximum low-level output current (IOL): VCC= 1.65 V 4 mA VCC= 2.3 V 12 mA VCC= 2.7

12、V 12 mA VCC= 3 V . 24 mA Maximum input transition rise or fall rate (t/v) . 5 ns/V Operating free-air temperature range (TA) -40C to +85C 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation

13、 of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input negative-voltage and output voltage ratings may be exceeded i

14、f the input and output current ratings are observed. 3/ This value is limited to 4.6 V maximum. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo

15、 reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04762 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semi

16、conductor Devices JEDEC STD 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQU

17、IREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with th

18、e manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. Th

19、e design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Function table. The function table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in fig

20、ure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-D

21、EFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04762 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature, TALimits Unit Min Max High level output voltage VOHIOH= -100 A 1.65 V to 3.6 V 25C, -40C to 85C VCC 0.2

22、V IOH= -4 mA 1.65 V 1.2 IOH= -6 mA 2.3 V 2 IOH= -12 mA 2.3 V 1.7 2.7 V 2.2 3 V 2.4 IOH= -24 mA 3 V 2 Low level output voltage VOLIOL= 100 A 1.65 V to 3.6 V 0.2 V IOL= 4 mA 1.65 V 0.45 IOL= 6 mA 2.3 V 0.4 IOL= 12 mA 2.3 V 0.7 2.7 V 0.4 IOL= 24 mA 3 V 0.55 Input current IIVI= VCCor GND 3.6V 5 A Off-st

23、ate output current IOZVO= VCCor GND 3.6 V 10 A Quiescent supply current ICCVI= VCCor GND, IO= 0 A 3.6 V 10 A Quiescent supply current delta ICCOne input at VCC 0.6 V, Other inputs at VCCor GND 3 V to 3.6 V 750 A Input capacitance CIControl inputs and data inputs VI= VCCor GND 3.3 V 25C 4.5 TYP pF Ou

24、tput capacitance COVO= VCCor GND 3.3 V 7.5 TYP pF Power dissipation capacitance per buffer/driver CpdOutputs enabled CL= 0 pF f = 10 MHz 1.8 V 25C 22 TYP pF 2.5 V 23 TYP 3.3 V 26 TYP Outputs disabled CL= 0 pF f = 10 MHz 1.8 V 1 TYP 2.5 V 1 TYP 3.3 V 1 TYP Propagation delay time, A to Y tpdSee figure

25、 5. 1.8 V 0.15 V 25C, -40C to 85C 1 4.4 ns 2.5 V 0.2 V 1 3.1 2.7 V 3.1 3.3 V 0.3 V 1.1 2.8 Propagation delay time, output enable, OE to Y tenSee figure 5. 1.8 V 0.15 V 1.8 6.9 2.5 V 0.2 V 1.5 5.4 2.7 V 5.3 3.3 V 0.3 V 1.5 4.5 Propagation delay time, output disable, OE to Y tdisSee figure 5. 1.8 V 0.

26、15 V 1.8 5.9 2.5 V 0.2 V 1 4.1 2.7 V 4.4 3.3 V 0.3 V 1.7 4.2 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all par

27、ameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZ

28、E A CODE IDENT NO. 16236 DWG NO. V62/04762 REV A PAGE 6 Case X Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A - 1.20 - .047 E 4.30 4.50 .169 .177 A1 0.05 0.15 .002 .006 E1 6.20 6.60 .244 .260 b 0.19 0.30 .007 .012 e 0.65 BSC .026 BSC c 0.15 NOM .006

29、NOM L 0.50 0.75 .020 .030 D 6.40 6.60 .252 .260 NOTES: 1. This drawing is subject to change without notice. 2. Falls within JEDEC MO-153. 3. All linear dimensions are shown in millimeters (inches). Inches equivalents are given for general information only. 4. Body dimensions do not include mold flas

30、h or protrusion not to exceed 0.15 millimeters (0.006 inches). FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04762 REV A PAGE 7 (each buf

31、fer/driver) Inputs Output Y OE A L L H H L X H L Z H = High voltage level X = Immaterial L = Low voltage level Z = High impedance state FIGURE 2. Function table. FIGURE 3. Logic diagram. Device type 01 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 1OE11 2A1 2 1A1 1

32、2 1Y4 3 2Y4 13 2A2 4 1A2 14 1Y3 5 2Y3 15 2A3 6 1A3 16 1Y2 7 2Y2 17 2A4 8 1A4 18 1Y1 9 2Y1 19 2OE10 GND 20 VCCFIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE ID

33、ENT NO. 16236 DWG NO. V62/04762 REV A PAGE 8 NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is h

34、igh, except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO= 50. 4. The outputs are measured one at a time, with one input transition per measurement. 5. tPLHand tPHLare the same as tpd. 6. tPZLand tPZHare the sa

35、me as ten. 7. tPLZand tPHZare the same as tdis. FIGURE 5. Timing waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04762 REV A PAGE 9 4.

36、VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labelin

37、g of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electros

38、tatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be mo

39、dified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device man

40、ufacturer CAGE code Vendor part number Top-Side Marking V62/04762-01XE 01295 SN74ALVC244IPWREP VA244IEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-