DLA DSCC-VID-V62 05609 REV B-2012 MICROCIRCUIT LINEAR 1 8 GHz LOW DISTORTION CURRENT FEEDBACK AMPLIFIER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add test conditions to the table I. - phn 08-07-09 Thomas M. Hess B Add footnote to paragraphs 1.2.2 and 6.3. Table I, VS= 7.5 V condition, make changes to open loop transimpedance gain, input bias current (inverting and non inverting), common mode rejectio

2、n ratio, voltage output swing, and positive power supply rejection ratio test limits. Table I, VS= 5.0 V condition, make changes to open loop transimpedance gain, input offset voltage, input bias current (inverting and non inverting), common mode rejection ratio, current output sinking, and positive

3、 power supply rejection ratio test limits. Make corrections to A1 and c dimensions under case X. Make corrections to all dimensions under case Y. - ro 12-06-14 Charles F. Saffle CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in

4、accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY Phu H. Nguyen TIT

5、LE MICROCIRCUIT, LINEAR, 1.8 GHz, LOW DISTORTION, CURRENT FEEDBACK AMPLIFIER, MONOLITHIC SILICON 05-06-14 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/05609 REV B PAGE 1 OF 12 AMSC N/A 5962-V018-12Provided by IHSNot for ResaleNo reproduction or networking permitted without lic

6、ense from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05609 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 1.8 GHz, low distortion, current feedback amplifier, with an operating temperature ran

7、ge of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/05609 - 01 X E Drawing Device type Case

8、 outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device type Generic Circuit function 01 THS3201-EP 1.8 GHz, low distortion, current feedback amplifier 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB

9、95 Package style X 8 JEDEC MS-012 Plastic small outline package Y 2/ 8 JEDEC M0-187 Plastic small outline package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C

10、 Gold plate D Palladium E Gold flash palladium Z Other 1/ Users are cautioned to review the manufacturers data manual for additional user information relating to this device. 2/ The manufacture has changed lead frames NiPdAu to NiPdAuAg and location of assembly from their Hana facility to their Shan

11、ghai facility. Product with a Lot Trace Code of 1CxxxxH and earlier is a NiPdAu frame from the Hana facility. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05609

12、 REV B PAGE 3 1.3 Absolute maximum ratings. 3/ Supply voltage, (VS) . +16.5 V Input voltage, (VI): . VSOutput current, (IO) . 175 mA Differential input voltage, (VID) 3.0 V Maximum junction temperature, (TJ) +150C 4/ Maximum junction temperature, continuous operation, long term reliability, (TJ) . +

13、125C 5/ Storage temperature range, (TSTG) . -65C to +150C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds . +300C ESD ratings: HBM . +3000 V CDM . +1500 V MM . +100 V Package dissipation ratings: Package JC(C/W) JA 6/ (C/W) Case X 38.3 97.5 Case Y 7/ 4.7 58.4 1.4 Recommended operating c

14、onditions. Supply voltage: Maximum dual supply 3.3 V to 7.5 V Single supply +6.6 V to +15.0 V Operating free air temperature range, (TA) -55C to +125C 3/ Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may affect device reliabilit

15、y. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. 4/ The absolute maximum temperature under any condition is limited by the constraints of the silicon process. Stresses above these ratings may cause perman

16、ent damage. Exposure to absolute maximum conditions for extended periods may affect device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. 5/ Long term high temperature storage and/or extended

17、used at maximum recommended operating conditions may result in a reduction of overall device life. See figure 3 for additional information on thermal derating. 6/ This data was taken using the JEDEC standard high K test PCB. 7/ The devices on this drawing may incorporate a thermal pad on the undersi

18、de of the chip. This act as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. Refer to the manufacturer for more information about utiliz

19、ing the thermally enhanced package. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05609 REV B PAGE 4 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Associa

20、tion JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the JEDEC Office, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and l

21、egibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if

22、 applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as

23、 specified herein. 3.5 Diagrams. 3.5.1 Case outlines. The case outlines shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Wirebond life versus temperature. Wirebond life versus temperature shall be as shown in figure 3.

24、 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05609 REV B PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Test condition VS= 7.5 V, G = +2 Rf =

25、1 k, RL= 100 unless otherwise noted Device type: All Limits Unit Min/ Typ/ Max Typ Over temperature 25C 25C -55C to +125C AC Performance Small signal bandwidth, -3 dB (VO= 200 mVPP) G = +1, Rf= 1.2 k 1.8 GHz Typ G = +2, Rf= 768 850 MHz G = +5, Rf= 619 565 G = +10, Rf= 487 520 Bandwidth for 0.1 dB fl

26、atness G = +2, VO= 200 mVPP,Rf= 768 380 MHz Large signal bandwidth G = +2, VO= 2 VPP,Rf= 715 880 MHz Slew rate G = +2, VO= 5-V step, Rf= 768 , Rise/Fall 5400/ 4000 V/s G = +2, VO= 10-V step, Rf= 768 , Rise/Fall 9800/ 6700 Rise and fall time G = +2, VO= 4-V step, Rf= 768 , Rise/Fall 0.7/ 0.9 ns Setti

27、ng time to 0.1% G = -2, VO= 2-V step 20 Setting time to 0.01% 60 Harmonic distortion 2ndharmonic G = +5, f = 10 MHz, VO= 2 VPPRL= 100 -64 dBc 3rdharmonic RL= 100 -73 Third order intermodulation distortion (IMD3) G = +10, fc= 100 MHz, f = 1 MHz, VO(envelope)= 2 VPP-78 Noise figure G = +10, fc = 100 M

28、Hz, RF= 255 RG= 28 11 dB Input voltage noise f 10 MHz 1.65 nV/ Hz Input current noise (non inverting) f 10 MHz 13.4 pA/ Hz Input current noise (inverting) 20 Differential gain G = +2, RL= 150 , Rf= 768 NTSC 0.008% PAL 0.004% Differential phase NTSC 0.007 PAL 0.011 See notes at end of table. Provided

29、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05609 REV B PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Test Test condition VS= 7.5 V, G = +2 Rf =

30、 1 k, RL= 100 Single ended input unless otherwise noted Device type: All Limits Unit Min/ Typ/ Max Typ Over temperature 25C 25C -55C to +125C DC performance Open loop transimpedance gain VO= 4 V, RL= 1 k 300 200 100 k Min Input offset voltage VCM= 0 V, RL= 1 k 0.7 4 6 mV Max Average offset voltage d

31、rift 13 V/C Typ Input bias current (inverting) 13 65 90 A Max Average bias current drift (-) 400 nA/C Typ Input bias current (non inverting) 14 40 60 A Max Average bias current drift (+) 400 nA/C Typ Input Common mode input range RL= 1 k 5.1 5 5 V Min Common mode rejection ratio VCM= 3.75 V 71 58 53

32、 dB Min Inverting input impedance, ZinOpen loop 16 Typ Input resistance Non inverting 780 k Inverting 11 Input capacitance Non inverting 1 pF Output Voltage output swing RL= 1 k 6 5.9 5.7 V Min RL= 100 5.8 5.7 5.35 V Min Current output, sourcing RL= 20 115 105 100 mA Min Current output sinking 100 8

33、5 80 mA Min Closed loop output impedance G = +1, f = 1 MHz 0.01 Typ Power supply Minimum operating voltage 3.3 3.3 V Min Maximum operating voltage 7.5 7.5 V Max Maximum quiescent current 14 18 22 mA Max Power supply rejection (+PSRR) VS+ = 7 V to 8 V, RL= 1 k 69 60 56 dB Min Power supply rejection (

34、-PSRR) VS- = -7 V to -8 V, RL= 1 k 65 58 55 dB Min See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05609 REV B PAGE 7 TABLE I. Electrica

35、l performance characteristics.- Continued. 1/ Test Test condition VS= 5.0 V, G = +2 Rf = 1 k, RL= 100 Single ended input unless otherwise noted Device type: All Limits Unit Min/ Typ/ Max Typ Over temperature 25C 25C -55C to +125C AC Performance Small signal bandwidth, -3 dB (VO= 200 mVPP) G = +1, Rf

36、= 1.2 k 1.3 GHz Typ G = +2, Rf= 715 725 MHz G = +5, Rf= 576 540 G = +10, Rf= 464 480 Bandwidth for 0.1 dB flatness G = +2, VO= 200 mVPP,Rf= 715 170 MHz Large signal bandwidth G = +2, VO= 2 VPP,Rf= 715 900 MHz Slew rate G = +2, VO= 5-V step, Rf= 715 , Rise/Fall 5200/ 4000 V/s Rise and fall time G = +

37、2, VO= 4-V step, Rf= 715 , Rise/Fall 0.7/ 0.9 ns Setting time to 0.1% G = -2, VO= 2-V step 20 Setting time to 0.01% 60 Harmonic distortion 2ndharmonic G = +5, f = 10 MHz, VO= 2 VPPRL= 100 -69 dBc 3rdharmonic RL= 100 -75 Third order intermodulation distortion (IMD3) G = +10, fc = 20 MHz, f = 1 MHz, V

38、O(envelope)= 2 VPP-81 Noise figure G = +10, , fc = 100 MHz, RF= 255 RG= 28 11 dB Input voltage noise f 10 MHz 1.65 nV/ Hz Input current noise (non inverting) f 10 MHz 13.4 pA/ Hz Input current noise (inverting) 20 Differential gain G = +2, RL= 150 , Rf= 768 NTSC 0.006% PAL 0.004% Differential phase

39、NTSC 0.03 PAL 0.04 See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05609 REV B PAGE 8 TABLE I. Electrical performance characteristics Co

40、ntinued. 1/ Test Test condition VS= 5.0 V, G = +2 Rf = 1 k, RL= 100 Single ended input unless otherwise noted Device type: All Limits Unit Min/ Typ/ Max Typ Over temperature 25C 25C -55C to +125C DC performance Open loop transimpedance gain VO= 2 V, RL= 1 k 300 200 100 k Min Input offset voltage VCM

41、= 0 V, RL= 1 k 0.7 3 5.5 mV Max Average offset voltage drift 13 V/C Typ Input bias current (inverting) 13 65 90 A Max Average bias current drift (-) 400 nA/C Typ Input bias current (non inverting) 14 40 60 A Max Average bias current drift (+) 400 nA/C Typ Input Common mode input range RL= 1 k 2.6 2.

42、5 2.5 V Min Common mode rejection ratio VCM= 2.5 V 71 56 50 dB Min Inverting input impedance, ZinOpen loop, RL= 1 k 17.5 Typ Input resistance Non inverting 780 k Inverting 11 Input capacitance Non inverting 1 pF Output Voltage output swing RL= 1 k 3.65 3.5 3.4 V Min RL= 100 3.45 3.33 3.2 V Min Curre

43、nt output, sourcing RL= 20 115 105 90 mA Min Current output sinking 100 80 75 mA Min Closed loop output impedance G = +1, f = 1 MHz 0.01 Typ Power supply Minimum operating voltage 3.3 3.3 V Min Maximum operating voltage 7.5 7.5 V Max Maximum quiescent current 14 16.8 20.5 mA Max Power supply rejecti

44、on (+PSRR) VS+ = 4.5 V to 5.5 V, RL= 1 k 69 60 56 dB Min Power supply rejection (-PSRR) VS- = -4.5 V to -5.5 V, RL= 1 k 65 58 55 dB Min 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product

45、may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. Provided by IHSNot for ResaleNo reproduction or networking permitted with

46、out license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05609 REV B PAGE 9 Case X Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A 1.75 .069 D 4.80 5.00 .189 .197 A1 0.10 0.25 .004 .010 E 3.80 4.00 .150 .157

47、 A2 0.25 BSC .010 BSC E1 5.80 6.20 .228 .244 b 0.31 0.51 .012 .020 e 1.27 BSC .050 BSC c 0.13 0.25 .005 .010 L 0.40 1.27 .016 .050 Notes: 1. Controlling dimensions are millimeter, inch dimensions are given for reference only. 2. For dimension D, body length does not include mold flash, protrusion, or gate burrs. Mold flash, protrusion, or gate burrs shall not exceed 0.006 inch (0.15 mm) each side. 3. For dimension E, body width does not include interlead flash. Interlead flash shall not exceed