DLA DSCC-VID-V62 06602 REV A-2012 MICROCIRCUIT DIGITAL-LINEAR 2 7 V TO 5 5 V 12 BIT 3 祍 QUADRUPLE DIGITAL TO ANALOG CONVERTER WITH POWER DOWN MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 12-01-19 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing RE

2、V PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL-LINEAR, 2.7 V TO 5.5 V 12 BIT 3 s Q

3、UADRUPLE DIGITAL TO ANALOG CONVERTER WITH POWER DOWN, MONOLITHIC SILICON 06-08-09 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/06602 REV A PAGE 1 OF 12 AMSC N/A 5962-V025-12 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFE

4、NSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06602 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 2.7 V to 5.5 V 12 bit 3 s quadruple digital to analog converter with power down microcircuit, with an operat

5、ing temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/06602 - 01 X E Drawi

6、ng Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TLV5614-EP 2.7 V to 5.5 V 12 bit 3 s quadruple digital to analog converter with power down 1.2.2 Case outline(s). The case outlines are as specified herein

7、. Outline letter Number of pins JEDEC PUB 95 Package style X 16 MO-153 Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladi

8、um E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage ( DVDD, AVDDto GND) . 7.0 V Supply voltage difference (AVDDto DVDD) -2.8 V to 2.8 V Digital input voltage range . -0.3 V to DVDD+ 0.3 V Reference input voltage range . -0.3 V to AVDD+ 0.3 V Operating free-air temperatu

9、re range ( TA) -55C to +125C Storage temperature range (TSTG) . -65C to 150C Lead temperature 1.6 mm (1/16 in) from case for 10 s 260C _ 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation

10、of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted withou

11、t license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06602 REV A PAGE 3 1.4 Recommended operating conditions. Supply voltage range (AVDD, DVDD): 5 V supply . 4.5 V to 5.5 V 3 V supply . 2.7 V to 3.3 V Minimum high level digital input voltage(V

12、IH): DVDD= 2.7 V . 2.0 V DVDD= 5.5 V . 2.4 V Maximum low level digital input voltage(VIL): DVDD= 2.7 V . 0.6 V DVDD= 5.5 V . 1.0 V Reference voltage, Vrefto REFINAB, REFINCD terminal: 5 V supply 2/ . 0.0 V to VDD 1.5 V 3 V supply 2/ . 0.0 V to VDD 1.5 V Minimum load resistance, (RL) . 2 k Maximum lo

13、ad capacitance, (CL) . 100 pF Maximum serial clock rate, (SCLK) 20 MHz Operating free-air temperature range ( TA) -55C to +125C Typical package thermal resistance, junction to ambient (JA) 108C/W 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Sta

14、ndard Outlines for Semiconductor Devices JEDEC STD 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arling

15、ton, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container

16、shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and

17、 physical dimension. The design, construction, and physical dimensions are as specified herein. 2/ Voltages greater than AVDD/2 cause output saturation for large DAC codes. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMB

18、US COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06602 REV A PAGE 4 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Functional block diagram. The functional

19、block diagram shall be as shown in figure 3. 3.5.4 Operating life derating chart. The operating life derating chart shall be as shown in figure 4. 3.5.5 Power down supply current . The power down supply current shall be as shown in figure 5. 3.5.6 Timing diagram. The timing diagram shall be as shown

20、 in figure 6. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06602 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions -55C TA

21、 125C Vref= 2.048 V for AVDD= DVDD= 5.0 V Vref= 1.024 V for AVDD= DVDD= 3.0 V unless otherwise specified Limits Unit Min Max Resolution 12 bits Integral nonlinarity (INL), end point adjusted 2/ 4 LSB Differential nonlinearity (DNL) 3/ 1 Zero scale error (offset error at zero scale) EZS4/ 12 mV Zero

22、scale error temperature coefficient 5/ 10 Typ ppm/C Gain error 6/ 0.7 % of FS voltage Gain error temperature coefficient 7/ 10 Typ ppm/C Power supply rejection ratio Zero scale 8/ 9/ -80 Typ dB Full scale -80 Typ Individual DAC output specifications Voltage output range VORL= 10 k 0 AVDD 0.4 V Outpu

23、t load regulation accuracy RL= 2 k vs 10 k 0.25 % of FS voltage Reference inputs (REFINAB, REFINCD) Input voltage range VI10/ 0 AVDD 1.5 V Input resistance RI10 Typ M Input capacitance CI5 Typ pF Reference feed through REFIN = 1 VPPat 1 kHz + 1.024 Vdc 11/ -75 Typ dB Reference input bandwidth REFIN

24、= 0.2 VPP+ 1.024 Vdc large signal Slow 0.5 Typ MHz Fast 1 Typ Digital inputs (DIN, CS , LDAC , PD ) High level digital input current IIHVI= VDD1 A Low level digital input current IILVI= 0 V 1 Input capacitance CI3 Typ pF Power supply Power supply current IDD5-V supply, No load, Clock running, All in

25、puts 0 V or VDDSlow 2.4 mA Fast 5.6 3-V supply, No load, Clock running, All inputs 0 V or VDDSlow 1.8 Fast 4.8 Power down supply current See figure 5 10 Typ nA See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUP

26、PLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06602 REV A PAGE 6 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions -55C TA 125C Vref= 2.048 V for AVDD= DVDD= 5.0 V Vref= 1.024 V for AVDD= DVDD= 3.0 V unless otherwise specified Limits Unit

27、 Min Max Analog output dynamic performance Output slew rate SR CL= 100 pF, VO= 10% to 90% RL= 10 k, Vref= 2.048 V, 1.024 V Slow 5 Typ V/s Fast 1 Typ Output setting time tSTo 0.5 LSB, CL= 100 pF, RL= 10 k, 12/ Slow 3 Typ s Fast 9 Typ Output setting time, code to code tS(C)To 0.5 LSB, CL= 100 pF, RL=

28、10 k, 13/ Slow 1 Typ Fast 2 Typ Glitch energy Code transition from 7FF to 800 10 Typ nV-s Signal to noise ratio SNR Sine wave generated by DAC, Reference voltage = 1.024 at 3 V and 2.048 at 5 V, fs= 400 KSPS, fOUT= 1.1 kHz sine wave, CL= 100 pF, RL= 10 k, BW = 20 kHz 74 Typ dB Signal to noise + dist

29、ortion S/(N+D) 66 Typ Total harmonic distortion THD -68 Typ Spurious free dynamic range SFDR 70 Typ Digital input timing requirements Setup time, CS low before FS tsu(CS-FS) See figure 6. 10 ns Setup time, FS low before first negative SCLK edge tsu(FS-CK)8 Setup time, sixteenth negative SCLK edge af

30、ter FS low on which bit D0 is sampled before rising edge of FS tsu(C16-FS)10 Setup time. The first positive SCLK edge after D0 is sampled before CS rising edge. If FS is used instead of the SCLK positive edge to update DAC, then the setup time is between the FS rising edge and CS rising edge. tsu(C1

31、6-CS)10 Pulse duration, SCLK high twH25 Pulse duration, SCLK low twL25 Setup time, data ready before SCLK falling edge. tsu(D)8 Hold time, data held valid after SCLK falling edge. th(D)5 Pulse duration, FS high twH(FS)60 Typ See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction

32、 or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06602 REV A PAGE 7 TABLE I. Electrical performance characteristics Continued. 1/ Testing and other quality control techniques are used to the extent deemed nec

33、essary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/o

34、r design. 2/ The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full scale errors. 3/ The differential nonlinearity (DNL), sometimes re

35、ferred to as differential error, is the difference between the measured and ideal 1-LSB amplitude change of any two adjacent codes. Monotonis means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 4/ Zero scale error is th deviation from z

36、ero voltage output when the digital input code is zero. 5/ Zero error scale error temperature coefficient is given by: EZSTC = EZS(Tmax) EZS(Tmin)/Vrefx 106/(Tmax- Tmin). 6/ Gain error is the deviation from the ideal output (2Vref 1 LSB) with an output load of 10 k, excluding the effects of the zero

37、 error. 7/ Gain temperature coefficient is given by: EGTC = EG(Tmax) EG(Tmin)/Vrefx 106/(Tmax- Tmin). 8/ Zero scale error rejection ratio (EZS-RR) is measured by varying the AVDDfrom 5 0.5 V and 3 0.3 V dc, and measuring the proportion of this signal imposed on the zero code output voltage. 9/ Full

38、scale rejection ratio (EG-RR) ) is measured by varying the AVDDfrom 5 0.5 V and 3 0.3 V dc, and measuring the proportion of this signal imposed on the full scale output voltage after subtracting the zero scale change. 10/ Reference input voltages greater than VDD/2 cause output saturation for large

39、DAC codes. 11/ Reference feed through is measured at the DAC output, with an input code = 000 hex and a Vref (REFINAB or REFINCD)input = 1.024 Vdc + 1 VPPat 1 kHz. 12/ Setting time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change

40、of FFF hex to 080 hex for 080 hex to FFF hex. 13/ Setting time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of one count. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENS

41、E SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06602 REV A PAGE 8 Case X Dimension Symbol Millimeters Symbol Millimeters Min Max Min Max A 1.45 E 1.45 1.75 A1 0.00 0.15 E1 2.60 3.00 b 0.30 0.50 e 0.95 NOM c 0.08 0.22 L 0.30 0.55 D 2.75 3.05 NOTES: 1. This drawing is

42、 subject to change without notice. 2. Body dimensions do not include mold flash or protrusion not to exceed 0.15 mm (0.006 inches). 3. Falls within JEDEC MO-153. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY C

43、ENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06602 REV A PAGE 9 Case X Terminal number Terminal symbol Terminal number Terminal symbol 1 DVDD9 AGND 2 PD 10 REFINCD 3 LDAC 11 OUTD 4 DIN 12 OUTC 5 SCLK 13 OUTB 6 CS 14 OUTA 7 FS 15 REFINAB 8 DGND 16 AVDDFIGURE 2. Terminal conn

44、ections. FIGURE 3. Functional block diagram Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06602 REV A PAGE 10 FIGURE 4. Operating life derating chart. FIGURE 5.

45、Power down supply current. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06602 REV A PAGE 11 FIGURE 6. Timing diagram. Provided by IHSNot for ResaleNo reproducti

46、on or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06602 REV A PAGE 12 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements a

47、s indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The da