DLA DSCC-VID-V62 06603 REV A-2012 MICROCIRCUIT DIGITAL PARALLEL LOAD 8-BIT SHIFT REGISTER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 12-01-19 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing RE

2、V PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, PARALLEL LOAD 8-BIT SHIFT REGISTER, MON

3、OLITHIC SILICON 06-03-09 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/06603 REV A PAGE 1 OF 11 AMSC N/A 5962-V026-12 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE ID

4、ENT NO. 16236 DWG NO. V62/06603 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance parallel load 8-bit shift register microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The man

5、ufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/06603 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s

6、). Device type Generic Circuit function 01 SN74LV165A-EP Parallel load 8-bit Shift Register 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 MO-153 Plastic small outline 1.2.3 Lead finishes. The lead finishes are as speci

7、fied below or other lead finishes as provided by the device manufactureR: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range ( VCC) -0.5 V to 7 V Input voltage range ( VI) -0.5 V t

8、o 7 V 2/ Voltage range applied to any output in the high impedance or power off state ( VO) . -0.5 V to 7 V 2/ Output voltage range ( VO) . -0.5 V to VCC+0.5 V 2/ 3/ Input clamp current ( IIK) ( VI 0 ) -20 mA Output clamp current ( IOK) ( VO 0 ) . -50 mA Continuous output current ( IO) ( VO= 0 to VC

9、C) . 25 mA Continuous current through VCCor GND 50 mA Package thermal impedance ( JA) 108C/W 4/ Storage temperature range (TSTG) . -65C to 150C _ 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional o

10、peration of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if the inp

11、ut and output current ratings are observed. 3/ This value is limited to 5.5 V maximum. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMB

12、US, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06603 REV A PAGE 3 1.4 Recommended operating conditions. 5/ Supply voltage range ( VCC) 2.0 V to 5.5 V Minimum high level input voltage ( VIH): VCC= 2 V . 1.5 V VCC= 2.3 V to 2.7 V VCCx 0.7 V VCC= 3 V to 3.6 V . VCCx 0.7 V VCC= 4.5 V to 5.5 V VCCx 0.7

13、 V Maximum low level input voltage ( VIL): VCC= 2 V . 0.5 V VCC= 2.3 V to 2.7 V VCCx 0.3 V VCC= 3 V to 3.6 V . VCCx 0.3 V VCC= 4.5 V to 5.5 V VCCx 0.3 V Input voltage ( VI) 0 V to 5.5 V Output voltage ( VO) . 0 V to VCCMaximum high level output current ( IOH): VCC= 2 V . -50 A VCC= 2.3 V to 2.7 V -2

14、 mA VCC= 3 V to 3.6 V . -6 mA VCC= 4.5 V to 5.5 V -12 mA Maximum low level output current ( IOL): VCC= 2 V . 50 A VCC= 2.3 V to 2.7 V 2 mA VCC= 3 V to 3.6 V . 6 mA VCC= 4.5 V to 5.5 V 12 mA Maximum input transition rise or fall rate ( t / v ): VCC= 2.3 V to 2.7 V 200 ns/V VCC= 3 V to 3.6 V . 100 ns/

15、V VCC= 4.5 V to 5.5 V 20 ns/V Operating free-air temperature range ( TA) -55C to +125C 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENT

16、ER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06603 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.o

17、rg or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or log

18、o B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance

19、characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal co

20、nnections. The terminal connections shall be as shown in figure 2. 3.5.3 Function table. The Function table shall be as shown in figure 3. 3.5.4 Logic diagram. The logic diagram shall be as shown in figure 4. 3.5.5 Load circuit and timing waveforms. The load circuit and timing waveforms shall be as

21、shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06603 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions -5

22、5C TA 125C unless otherwise specified VCCLimits Unit Min Max High level output voltage VOHIOH= -50 A 2.0 V to 5.5 V VCC 0.1 V IOH= -2 mA 2.3 V 2 IOH= -6 mA 3.0 V 2.48 IOH= -12 mA 4.5 V 3.8 Low level output voltage VOLIOL= 50 A 2.0 V to 5.5 V 0.1 V IOL= 2 mA 2.3 V 0.4 IOL= 6 mA 3.0 V 0.44 IOL= 12 mA

23、4.5 V 0.55 Input current IIVI= 5.5 V or GND 0 to 5.5 V 1 A Supply current ICCVI= VCCor GND, IO= 0, 5.5V 20 A Off current IoffVIor VO= 0 to 5.5 V 0 5 A Input capacitance CiVI= VCCor GND 3.3 V 1.7 Typ pF Power dissipation capacitance CpdCL= 50 pF, f = 10 MHz, TA= 25C 3.3 V 36.1 Typ 5.0 V 37.5 Typ Timi

24、ng Requirements Test Symbol Conditions VCCTA= 25C -55C TA 125C Unit Min Max Min Max Pulse duration tWCLK clock high or low 2.5 V 0.2 V 8.5 9 ns SH/ LD low 11 13 Setup time tSUSH/ LD high before CLK 7 8.5 SER before CLK 8.5 9.5 CLK INH before CLK 7 7 Data before SH/ LD 11.5 12 Hold time tHSER data af

25、ter CLK -1 0 Parallel data after SH/ LD 0 0.5 SH/ LD high after CLK 0 0 Pulse duration tWCLK clock high or low 3.3 V 0.3 V 6 7 ns SH/ LD low 7.5 9 Setup time tSUSH/ LD high before CLK 5 6 SER before CLK 5 6 CLK INH before CLK 5 5 Data before SH/ LD 7.5 8.5 Hold time tHSER data after CLK 0 0 Parallel

26、 data after SH/ LD 0.5 0.5 SH/ LD high after CLK 0 0 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06603 REV A PAGE 6 TABLE I. Ele

27、ctrical performance characteristics Continued. Timing Requirements Test Symbol Conditions VCCTA= 25C -55C TA 125C Unit Min Max Min Max Pulse duration tWCLK clock high or low 5.0 V 0.5 V 4 6.5 SH/ LD low 5 6.5 Setup time tSUSH/ LD high before CLK 4 4 SER before CLK 4 4 CLK INH before CLK 3.5 4.5 Data

28、 before SH/ LD 5 5 Hold time tHSER data after CLK 0.5 0.5 Parallel data after SH/ LD 1 1 SH/ LD high after CLK 0.5 0.5 Switching characteristics Maximum frequency fmaxCL= 50 pF 2.5 V 0.2 V 40 35 MHz Propagation delay time from input CLK to output QHor QHtpd23.3 1 26 ns Propagation delay time from in

29、put SH/ LD to output QHor QH25.1 1 28 Propagation delay time from input H to output QHor QH25.3 1 28 Maximum frequency fmax3.3 V 0.3 V 60 50 MHz Propagation delay time from input CLK to output QHor QHtpd14.9 1 16.9 ns Propagation delay time from input SH/ LD to output QHor QH19.3 1 22 Propagation de

30、lay time from input H to output QHor QH17.6 1 20 Maximum frequency fmax5.0 V 0.5 V 75 75 MHz Propagation delay time from input CLK to output QHor QHtpd11.9 1 13.5 ns Propagation delay time from input SH/ LD to output QHor QH11.9 1 13.5 Propagation delay time from input H to output QHor QH11 1 12.5 1

31、/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of speci

32、fic parametric testing, product performance is assured by characterization and/or design. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06603 REV A PAGE 7 Case X

33、 Dimension Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A 1.20 0.047 E 4.30 4.50 0.169 0.177 A1 0.05 0.15 0.002 0.006 E1 6.20 6.60 0.244 0.260 b 0.19 0.30 0.007 0.012 e 0.65 NOM 0.026 NOM c 0.15 NOM 0.006 NOM L 0.50 0.75 0.020 0.030 D 4.90 5.10 0.193 0.201 NOTE

34、S: 1. This drawing is subject to change without notice. 2. Body dimensions do not include mold flash or protrusion not to exceed 0.15 mm (0.006 inches). 3. Falls within JEDEC MO-153. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS

35、-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06603 REV A PAGE 8 Case X Terminal number Terminal symbol Terminal number Terminal symbol 1 SH/ LD 9 QH2 CLK 10 SER 3 E 11 A 4 F 12 B 5 G 13 C 6 H 14 D 7 QH15 CLK INH 8 GND 16 VCCFIGURE 2. Terminal connection

36、s. Inputs Operation SH/ LD CLK CLK INH L X X Parallel load H H X Q0H X H Q0H L Shift H L Shift FIGURE 3. Function table. FIGURE 4. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CO

37、DE IDENT NO. 16236 DWG NO. V62/06603 REV A PAGE 9 FIGURE 5. Load circuit and timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06603 REV A PAGE 10

38、NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output cont

39、rol. 3. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO= 50 ,tr 3 ns, and tf 3 ns. 4. The outputs are measured one at a time with one input transition per measurement. 5. tPLZand tPHZare the same as tdis. 6. tPZLand tPZHare the same as ten. 7. tPHLand

40、tPLHare the same as tpd. 8. All parameters and waveforms are not applicable to all devices. FIGURE 5. Load circuit and timing waveforms Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A C

41、ODE IDENT NO. 16236 DWG NO. V62/06603 REV A PAGE 11 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic se

42、nsitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sen

43、sitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right

44、to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor i

45、tem drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top side marking V62/06603-01XE 01295 SN74LV165AMPWREP LV165EP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-