DLA DSCC-VID-V62 06605 REV A-2013 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS DUAL POSITIVE-EDGE-TRIGGERED DTYPE FLIP-FLOP MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate to current MIL-PRF-38535 requirements. - PHN 13-12-11 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing

2、 REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, LOW VOLTAGE CMOS, DUAL POSITIVE

3、-EDGE-TRIGGERED D-TYPE FLIP-FLOP, MONOLITHIC SILICON YY-MM-DD 06-02-15 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/06605 REV A PAGE 1 OF 10 AMSC N/A 5962-V018-14 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY C

4、ENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06605 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance dual positive-edge-triggered D-type flip-flop microcircuit, with an operating temperature range of -55C to +125C. 1.2 Ve

5、ndor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/06605 - 01 X E Drawing Device type Case outline Lead finish number

6、 (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LV74A-EP Dual positive-edge-triggered D-type flip-flop 1.2.2 Case outlines. The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 14 MO-153 Plastic s

7、mall-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Provided by IHSNot for ResaleNo reproduction or netwo

8、rking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06605 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 7 V Input voltage range (VI) . -0.5 V to 7 V 2/ Output voltage range (VO) . -

9、0.5 V to VCC+ 0.5 V 2/ 3/ Voltage range applied to any output in the high-impedance or power-off state (VO) . -0.5 V to 7 V 2/ Input clamp current (IIK) (VI 0) -20 mA Output clamp current (IOK) (VO 0) . -50 mA Continuous output current (IO) (VO= 0 to VCC) 25 mA Continuous current through VCCor GND .

10、 50 mA Package thermal impedance (JA) . 113C/W 4/ Storage temperature range (TSTG) . -65C to 150C 1.4 Recommended operating conditions. 5/ Supply voltage range (VCC) . 2 V to 5.5 V Minimum high level input voltage (VIH): VCC= 2 V . 1.5 V VCC= 2.3 V to 2.7 V . VCCx 0.7 V VCC= 3 V to 3.6 V VCCx 0.7 V

11、VCC= 4.5 V to 5.5 V . VCCx 0.7 V Maximum low level input voltage (VIL): VCC= 2 V . 0.5 V VCC= 2.3 V to 2.7 V . VCCx 0.3 V VCC= 3 V to 3.6 V VCCx 0.3 V VCC= 4.5 V to 5.5 V . VCCx 0.3 V Input voltage range (VI) . 0.0 V to 5.5 V Output voltage range (VO) . 0.0 V to VCCMaximum high level output current

12、(IOH): VCC= 2 V . -50 A VCC= 2.3 V to 2.7 V . -2 mA VCC= 3 V to 3.6 V -6 mA VCC= 4.5 V to 5.5 V . -12 mA Maximum low level output current (IOL): VCC= 2 V . 50 A VCC= 2.3 V to 2.7 V . 2 mA VCC= 3 V to 3.6 V 6 mA VCC= 4.5 V to 5.5 V . 12 mA Maximum input transition rise or fall rate (t/v): VCC= 2.3 V

13、to 2.7 V . 200 ns/V VCC= 3 V to 3.6 V 100 ns/V VCC= 4.5 V to 5.5 V . 20 ns/V Operating free-air temperature range (TA) -55C to +125C _ 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of

14、 the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output negative-voltage ratings may be exceeded if the input

15、 and output current ratings are observed. 3/ This value is limited to 5.5 V maximum. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproducti

16、on or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06605 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices

17、JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2107). 3. REQUIREMENTS 3.1 Markin

18、g. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers par

19、t number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construct

20、ion, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal con

21、nections. The terminal connections shall be as shown in figure 4. 3.5.5 Test circuit and timing waveforms. The test circuit and timing waveforms shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COL

22、UMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06605 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature, TALimits Unit Min Max High level output voltage VOHIOH= -50 A 2 V to 5.5 V 25C, -55C to 125C VCC 0.1 V IOH= -2 mA 2.3 V 2 IOH= -6

23、 mA 3 V 2.48 IOH= -12 mA 4.5 V 3.8 Low level output voltage VOLIOL= 50 A 2 V to 5.5 V 0.1 V IOL= 2 mA 2.3 V 0.4 IOL= 6 mA 3 V 0.44 IOL= 12 mA 4.5 V 0.55 Input current IIVI= 5.5 V or GND 0 V to 5.5 V 1 A Quiescent supply current ICCVI= VCCor GND IO= 0 A 5.5 V 20 A Quiescent supply current delta ICCOn

24、e input at VCC 0.6 V, Other inputs at VCCor GND 2.7 V to 3.6 V 500 A Off-state current IoffVIor VO= 0 V to 5.5 V 0 V 5 A Input capacitance CiVI= VCCor GND 3.3 V 2 TYP pF 5 V 2 TYP Power dissipation capacitance CpdCL= 50 pF, f = 10 MHz 3.3 V 25C 21 TYP pF 5 V 23 TYP Quiet output, maximum dynamic VOLV

25、OL(P)2/ CL= 50 pF 3.3 V 25C 0.8 V Quiet output, minimum dynamic VOLVOL(V)2/ 3.3 V -0.8 V Quiet output, minimum dynamic VOHVOH(V)2/ 3.3 V 3.2 TYP V High-level dynamic input voltage VIH(D)2/ 3.3 V 2.31 V Low-level dynamic input voltage VIL(D)2/ 3.3 V 0.99 V Pulse duration twPREor CLRlow See figure 5.

26、2.5 V 0.2 V 25C 8 ns -55C to 125C 9 3.3 V 0.3 V 25C 6 -55C to 125C 7 5 V 0.5 V 25C 5 -55C to 125C 5 CLK See figure 5. 2.5 V 0.2 V 25C 8 -55C to 125C 9 3.3 V 0.3 V 25C 6 -55C to 125C 7 5 V 0.5 V 25C 5 -55C to 125C 5 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networ

27、king permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06605 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions VCCTemperature, TALimits Unit Min Max Setup time before CLK tsu

28、 Data See figure 5. 2.5 V 0.2 V 25C 8 ns -55C to 125C 9 3.3 V 0.3 V 25C 6 -55C to 125C 7 5 V 0.5 V 25C 5 -55C to 125C 5 PREor CLRinactive See figure 5. 2.5 V 0.2 V 25C 7 -55C to 125C 7 3.3 V 0.3 V 25C 5 -55C to 125C 5 5 V 0.5 V 25C 3 -55C to 125C 3 Hold time, data after CLK th See figure 5. 2.5 V 0.

29、2 V 25C 0.5 ns -55C to 125C 0.5 3.3 V 0.3 V 25C 1.45 -55C to 125C 2.15 5 V 0.5 V 25C 1.45 -55C to 125C 2.15 Maximum clock frequency fmaxCL= 50 pF See figure 5. 2.5 V 0.2 V 25C 30 MHz -55C to 125C 25 3.3 V 0.3 V 25C 50 -55C to 125C 45 5 V 0.5 V 25C 90 -55C to 125C 75 Propagation delay time, PREor CLR

30、to Q or QtpdCL= 50 pF See figure 5. 2.5 V 0.2 V 25C 17.4 ns -55C to 125C 20 3.3 V 0.3 V 25C 15.8 -55C to 125C 18 5 V 0.5 V 25C 9.7 -55C to 125C 12 Propagation delay time, CLK to Q or QtpdCL= 50 pF See figure 5. 2.5 V 0.2 V 25C 20 ns -55C to 125C 23 3.3 V 0.3 V 25C 15.4 -55C to 125C 18 5 V 0.5 V 25C

31、9.9 -55C to 125C 13 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In

32、 the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Characteristics are for surface-mount packages only. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COL

33、UMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06605 REV A PAGE 7 Case X Dimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max A - 0.047 - 1.20 E 0.169 0.177 4.30 4.50 A1 0.002 0.006 0.05 0.15 E1 0.244 0.260 6.20 6.60 b 0.007 0.012 0.19 0.30 e 0.026 BSC

34、0.65 BSC c 0.006 NOM 0.15 NOM L 0.020 0.030 0.50 0.75 D 0.193 0.201 4.90 5.10 NOTES: 1. All linear dimensions are in millimeters (inches). 2. This case outline is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion, not to exceed 0.15 mm (0.006 inches). 4. Fa

35、lls within JEDEC MO-153. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06605 REV A PAGE 8 Inputs Outputs PRE CLR CLK D Q Q L H L H H H H

36、L L H H H X X X L X X X H L X H L H 1/ H L Q0L H H 1/ L H Q0H = High voltage level L = Low voltage level X = Immaterial = Transition from low to high level. Q0or Q0= Level of Q before the indicated steady-state input conditions were established. 1/ This configuration is nonstable; that is, it does n

37、ot persist when PRE or CLR returns to its inactive (high) level. FIGURE 2. Truth table. FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06

38、605 REV A PAGE 9 Device type 01 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 1CLR 8 2Q 2 1D 9 2Q 3 1CLK 10 2PRE 4 1PRE 11 2CLK 5 1Q 12 2D 6 1Q 13 2CLR 7 GND 14 VCCFIGURE 4. Terminal connections. NOTES: 1. CLincludes probe and jig capacitance. 2. All input pulses a

39、re supplied by generators having the following characteristics: PRR 1 MHz, ZO= 50 , tr 3 ns, tf 3 ns. 3. The outputs are measured one at a time with one input transition per measurement. 4. tPLHand tPHLare the same as tpd. FIGURE 5. Test circuit and timing waveforms. Provided by IHSNot for ResaleNo

40、reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06605 REV A PAGE 10 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requ

41、irements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling

42、, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein i

43、s based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herei

44、n is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http:/www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number

45、1/ Device manufacturer CAGE code Vendor part number Top side marking V62/06605-01XE 01295 SN74LV74AMPWREP LV74AEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-