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本文(DLA DSCC-VID-V62 08610 REV A-2011 MICROCIRCUIT DIGITAL-LINEAR SINGLE SYNCHRONOUS BUCK PULSE MODULATION (PWM) CONTROLLER MONOLITHIC SILICON.pdf)为本站会员(towelfact221)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA DSCC-VID-V62 08610 REV A-2011 MICROCIRCUIT DIGITAL-LINEAR SINGLE SYNCHRONOUS BUCK PULSE MODULATION (PWM) CONTROLLER MONOLITHIC SILICON.pdf

1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Add device -01XE. Add case Y JClimit. - ro 11-01-04 C. SAFFLE CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATU

2、S OF PAGES REV A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL-LINEAR, SINGLE SYNCHRONOUS BUCK PULSE MODULAT

3、ION (PWM) CONTROLLER, MONOLITHIC SILICON 08-01-16 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/08610 REV A PAGE 1 OF 13 AMSC N/A 5962-V024-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUM

4、BUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08610 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance single synchronous buck pulse width modulation (PWM) controller microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendo

5、r Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/08610 - 01 X B Drawing Device type Case outline Lead finish number (S

6、ee 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 ISL6406 Single synchronous buck pulse width modulation (PWM) controller 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 N/A

7、Plastic quad flat Y 16 MO-153 Plastic thin shrink small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Othe

8、r Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08610 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range, ( VCC) +7.0 V Absolute boot voltage, (V

9、BOOT) . +15.0 V Upper driver supply voltage, VBOOT VPHASE. +6.0 V Input, Output or I/O voltage GND -0.3 V to VCC+0.3 V Maximum junction temperature range -55C to 150C 2/ Maximum storage temperature range -65C to 150C Thermal resistance, junction to ambient (JA) : Case X 35C/W 3/ Case Y 90C/W 4/ Ther

10、mal resistance, junction to case (JC) : Case X 4.5C/W 5/ Case Y (top) . 27C/W Electrostatic discharge (ESD) Class 2 1.4 Recommended operating conditions. Supply voltage range ( VCC) . 3.3 V 10% Operating free-air temperature range ( TA) . -55C to +125C 1/ Stresses beyond those listed under “absolute

11、 maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. 2/ Continuous operation at a TJ 125C and at maximum condi

12、tions will reduce the life expectancy of the device to as little as two years. 3/ JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See manufacturer data for more information. 4/ JA is measured with the component

13、mounted on a high effective thermal conductivity test board in free air. See manufacturer data for more information. 5/ JC, the “case temp” location is the center of the exposed metal pad on the package underside. Provided by IHSNot for ResaleNo reproduction or networking permitted without license f

14、rom IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08610 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the JEDEC Office, 3103 North 10th Stre

15、et, Suite 240-S, Arlington, VA 22201-2107 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS ident

16、ification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in

17、 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections

18、 shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as shown in figure 3. 3.5.4 RT versus frequency. RT versus frequency shall be as shown in figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER,

19、 COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08610 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ unless otherwise specified Limits Unit Min Typical Max VCCsupply section Shutdown supply current SYNC/EN = GND 20 55 A Operating supply cu

20、rrent 3/ RT = 64.9 k 6.5 9.8 11.5 mA Reference voltage section Nominal reference voltage 0.8 V Reference voltage tolerance -2.1 2.1 Error amplifier section Open loop voltage gain 4/ 82 dB Gain bandwidth product 4/ 14 MHz Slew rate 4/ COMP = 10 pF 4.65 6.0 9.2 V/s Charge pump section Nominal charge p

21、ump output VCC= 3.3 V, no load 4.7 5.1 5.5 V Charge pump output regulation -5.1 5.1 % Power on reset section Rising CPVOUT POR threshold 4.1 4.35 4.6 V CPVOUT POR threshold hysteresis 0.3 0.5 0.9 Oscillator section Gate output frequency range RT = 200 k 77 100 122 kHz RT = 64.9 k 247 300 341 RT = 26

22、.1 k 646 715 775 Sawtooth amplitude Peak-to-peak VOSC1.1 1.4 1.7 V Synchronous frequency range 4/ 1.1 times the natural switching frequency 110 770 kHz Minimum synchronous pulse width 4/ 40 100 ns PWM maximum duty cycle 96 % See footnote at end of table. Provided by IHSNot for ResaleNo reproduction

23、or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08610 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ unless otherwise specified Limits Unit Min Typical

24、Max Gate driver output section 4/ Upper gate source current VBOOT VPHASE= 4 V -1 A Upper gate sink current 1 A Lower gate source current VVCC= 3.3 V, VLGATE= 4 V -1 A Lower gate sink current 2 A Soft start section Soft start slew rate f = 300 kHz 6.2 6.7 7.8 ms Internal digital circuit clock count (

25、Soft start time varies with frequency) 2048 Clk cycles Overcurrent section OCSET current source 16 20 23 A 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested

26、 across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Over recommended operating conditions. All typical values are for TA= +25C and VCC= 3.3 V, unless o

27、therwise noted. 3/ This is the VCC current consumed when the device is active but not switching. 4/ Guaranteed by design. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG N

28、O. V62/08610 REV A PAGE 7 Case X Dimension Symbol Millimeters Symbol Millimeters Min Max Min Max A 0.80 1.00 D1/E1 4.75 BSC A1 0.05 e 0.80 BSC A2 1.00 e1 2.40 BSC b 0.28 0.40 S 0.35 0.75 D/E 5.00 BSC P 0.60 NOTES: 1. Dimension b applies to the metallized terminal and is measured between 0.15 mm and

29、0.30 mm from the terminal tip. 2. The configuration of the pin 1 identifier is optional, but must be located within the zone indicated. The pin 1 identifier may be either a mold or mark feature. 3. Nominal dimensions are provided to assist with printed circuit board land pattern design efforts, see

30、manufacturer data for more information. 4. Features and dimensions A2, D1, E1 and P are present when anvil singulation method is used and not present for saw singulation FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE

31、 SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08610 REV A PAGE 8 Case Y Dimension Symbol Millimeters Symbol Millimeters Min Max Min Max A 1.10 E 4.30 4.50 A1 0.05 0.15 e 0.65 BSC A2 0.80 1.05 E1 6.25 6.50 b 0.19 0.30 L 0.50 0.70 c 0.09 0.20 0o8oD 4.90 5.10 NOTES: 1.

32、 These package dimensions are within allowable dimensions of JEDEC MO-153 AB. 2. Dimensions “D and E1” do not include mold flash, interlead flash, protrusion or gate burrs. Mold flash, interlead flash, protrusion or gate burrs shall not exceed 0.15 mm per side. 3. “L” is the length of terminal for s

33、oldering to a substrate. 4. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08 mm total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07 mm. FIGURE 1. Case outlines Continued. Provided by IHS

34、Not for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08610 REV A PAGE 9 Terminal number Case X Case Y Terminal symbol Terminal symbol 1 CPVOUT GND 2 OCSET LGATE 3 CT1 CPVOUT 4 CT2 OCS

35、ET 5 RT CT1 6 SYNC/EN CT27 FB RT 8 VOUT SYNC/EN 9 COMP FB 10 CPGND VOUT 11 VCCCOMP 12 PHASE CPGND 13 BOOT VCC14 UGATE PHASE15 GND BOOT 16 LGATE UGATE FIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTE

36、R, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08610 REV A PAGE 10 Terminal symbol Terminal Description CPVOUT This pin represents the output of the charge pump. The voltage at this pin is the bias voltage for the integrated circuit. Connect a decoupling capacitor from this pin t

37、o ground. The value of the decoupling capacitor should be at least 10x the value of the charge pump capacitor. This pin may be tied to the bootstrap circuit as the source for creating the BOOT voltage. CT1, CT2 These pins are the connections for the external charge pump capacitor. A minimum of a 0.1

38、 F ceramic capacitor is recommended for proper operation of the integrated circuit. OCSET Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET(VIN). ROCSET, an internal 20 A current source (IOCSET), and the upper metal oxide semiconductor field effect transistor (MOSFET) on res

39、istance (rDS(ON) set the converter overcurrent (OC) trip point according to this equation: IPEAK= )ON(DSrOCSETOCSET)R)(I(An overcurrent trip cycles the soft start function. VOUT This pin is not used and should be left open. VCCThis pin provides bias supply for the integrated circuit. Connect a well

40、decoupled 3.3 V supply to this pin. PHASE Connect this pin to the upper MOSFETs source. This pin is used to monitor the voltage drop across the upper MOSFET for overcurrent protection. RT Connect an external resistor from this pin to ground for frequency selection. Refer to RT versus frequency curve

41、 shown in figure 4 BOOT This pin provides ground referenced bias voltage to the upper MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive a logic level N-Channel MOSFET. A large (1 M) resistor should be connected from the pin to GND. The purpose of this resistor is to di

42、scharge the BOOT pin during a shutdown condition, SYNC/EN = LOW so that the gate drivers are quickly powered off by this bleed resistor. UGATE Connect this pin to the upper MOSFETs gate. This pin provides the PWM controlled gate drive for the upper MOSFET. This pin is also monitored by the adaptive

43、shoot-through protection circuitry to determine when the upper MOSFET has turned off. GND This pin represents the signal and power ground for the integrated circuit. Tie this pin to the ground island/plane through the lowest impedance connection available. LGATE Connect this pin to the lower MOSFETs

44、 gate. This pin provides the PWM controlled gate drive for the lower MOSFET. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turned off. CMOP, FB COMP and FB are the available external pins of the error amplifier. The FB pin is the

45、 inverting input of the internal error amplifier and the COMP pin is the error amplifier output. These pins are used to compensate the control feedback loop of the converter. CPGND This pin represents the signal and power ground for the charge pump. Tie this pin to the ground island/plane through th

46、e lowest impedance connection available. SYNC/EN This is a dual function pin. To synchronize with an external clock, apply a clock with a frequency 1.1 to 2.0 times higher than the parts natural frequency to this pin. The device may be disabled by tying this pin to ground. In this shutdown mode, all

47、 functions are disabled and the device will draw 55 A supply current. FIGURE 2. Terminal connections - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08610 REV A PAGE 11 FIGURE 3. Block diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08610 REV A PAGE 12 FIGURE 4. RT versus frequency. Provid

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