DLA DSCC-VID-V62 08627-2008 MICROCIRCUIT DIGITAL HIGH SPEED ISOLATORS MONOLITHIC SILICON《单片硅高速隔离器数字微电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE 18 19 20 REV REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original d

2、ate of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA APPROVED BY ROBERT M. HEBER TITLE MICROCIRCUIT, DIGITAL, HIGH SPEED ISOLATORS, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/08627 08-07-29 REV PAGE 1 OF 20 AMSC N/A 5962-V050-08 Provided by IHSNot for ResaleNo reproduction or networki

3、ng permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08627 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance high speed isolator microcircuit, with an operating temperature

4、range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/08627 - 01 X E Drawing Device type C

5、ase outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 ISO721M-EP High speed isolator 02 ISO722M-EP High speed isolator 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PU

6、B 95 Package style X 8 MS-012-AA Plastic gullwing lead surface mount 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladiu

7、m Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08627 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range ( VCC1, VCC2) . -0.5 V to 6 V 2/ V

8、oltage at IN, OUT, or EN terminal -0.5 V to 6 V Output current (IO) . 15 mA Electrostatic discharge (ESD): Human body model (HBM) all pins . 2 kV Charged device model (CDM) all pins 1 kV Maximum junction temperature (TJ) . +170C Storage temperature range (TSTG). -65C to +150C 1.4 Recommended operati

9、ng conditions. 3/ Supply voltage: (VCC1) 4.5 V to 5.5 V (VCC2) 3 V to 3.6 V High level output current (IOH) . 4 mA maximum Low level output current (IOL) . -4 mA minimum High level input voltage (VIH) (IN, EN pins) 0.7 VCCto VCCLow level input voltage (VIL) (IN, EN pins) 0 V to 0.3 VCCInput pulse wi

10、dth (tui) . 6.67 ns minimum Junction temperature (TJ) +150C Operating free-air temperature range (TA) -55C to +125C 1.5 Thermal characteristics. Specified over recommended operating conditions unless otherwise noted. Parameter Symbol Test conditions Min Max Unit Junction to air JALow K thermal resis

11、tance 4/ 263 typical C/W High K thermal resistance 4/ 125 typical C/W Junction to board thermal resistance JB44 typical C/W Junction to case thermal resistance JC75 typical C/W Power dissipation PDVCC1= VCC2= 5.5 V, TJ= 150C, CL= 15 pF, input a 150 Mbps 50% duty cycle square wave 195 mW 1/ Stresses

12、beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-ma

13、ximum-rated conditions for extended periods may affect device reliability. 2/ All voltage values, except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. 3/ Use of this product beyond the manufacturers design rules or stated parameters is done at

14、 the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 4/ Tested in accordance with the low K or high K thermal metric definition of EIA / JESD51-3 for leaded surface mount packages. Provided by IHSNot for ResaleNo repr

15、oduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08627 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be add

16、ressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) IEC 60747-5-2 - Discrete semiconductor devices and integrated circuits Part 5-2: Optoelectronic devices Essential rating and characteristics IEC 61000-4-8 - Electromagnetic

17、 compatibility (EMC) Part 4-8: Testing and measurement techniques Power frequency magnetic field immunity test IEC 61000-4-9 - Electromagnetic compatibility (EMC) Part 4-9: Testing and measurement techniques Pulse magnetic field immunity test 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently a

18、nd legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C

19、 (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions ar

20、e as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Truth table. The truth table shall be as shown in figure 3. 3.5.4 Timing waveforms and test cir

21、cuits. The timing waveforms and test circuits shall be as shown in figures 4, 5, 6, 7, 8, and 9. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08627 REV PAGE 5 T

22、ABLE I. Electrical performance characteristics. 1/ Limits Test Symbol Conditions VCC1and VCC25 V operationTemperature, TADevice type Min Max Unit VCC1supply current ICC1Quiescent, VI= VCCor 0 V, no load -55C to +125C All 1 mA 25 Mbps, VI= VCCor 0 V, no load 4 VCC2supply current ICC2Quiescent, VI= VC

23、Cor 0 V, no load -55C to +125C All 12 mA 25 Mbps, VI= VCCor 0 V, no load 14 High level output voltage VOHIOH= -4 mA, see figure 4 -55C to +125C All VCC 0.8 V IOH= -20 A, see figure 4 VCC 0.1 Low level output voltage VOLIOH= 4 mA, see figure 4 -55C to +125C All 0.4 V IOH= 20 A, see figure 4 0.1 Input

24、 voltage hysteresis VI(HYS)+25C All 150 typical mV High level input current IIHIN at 2 V -55C to +125C All 10 A Low level input current IILIN at 0.8 V -55C to +125C All -10 A High impedance output current IOZEN , IN at VCC+25C 02 1 typical A Input capacitance to ground CIIN at VCC, VI= 0.4 sin (4E6t

25、) +25C All 1 typical pF Common mode transient immunity CMTI VI= VCCor 0 V, see figure 8 -55C to +125C All 25 kV/s See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A COD

26、E IDENT NO. 16236 DWG NO. V62/08627 REV PAGE 6 TABLE I. Electrical performance characteristics - continued. 1/ Limits Test Symbol Conditions VCC1and VCC25 V operationTemperature, TA Device type Min Max Unit Propagation delay, low to high level output tPLHEN at 0 V, see figure 4 -55C to +125C 01 2 16

27、 ns Propagation delay, high to low level output tPHLEN at 0 V, see figure 4 -55C to +125C 01 2 16 ns Pulse skew |tPHL tPLH| tsk(p)EN at 0 V, see figure 4 -55C to +125C 01 1 ns Part to part skew tsk(pp)2/ -55C to +125C All 3 ns Output signal rise time trEN at 0 V, see figure 4 +25C All 1 typical ns O

28、utput signal fall time tfEN at 0 V, see figure 4 +25C All 1 typical ns Sleep mode propagation delay, high level to high impedance output tPHZSee figure 5 +25C 02 8 typical ns Sleep mode propagation delay, high impedance to high level output tPZHSee figure 5 +25C 02 4 typical s Sleep mode propagation

29、 delay, low level to high impedance output tPLZSee figure 6 +25C 02 8 typical ns Sleep mode propagation delay, high impedance to low level output tPZLSee figure 6 +25C 02 5 typical s Failsafe output delay time from input power loss tfsSee figure 7 +25C All 3 typical s Peak to peak eye pattern jitter

30、 tjit(PP) 150 Mbps NRZ data input, see figure 9 +25C All 1 typical ns 150 Mbps unrestricted bit run length data input, see figure 9 2 typical ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COL

31、UMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08627 REV PAGE 7 TABLE I. Electrical performance characteristics continued. 1/ Limits Test Symbol Conditions VCC1at 5 V, VCC2at 3.3 V operationTemperature, TADevice type Min Max Unit VCC1supply current ICC1Quiescent, VI= VCCor 0 V, no load

32、 -55C to +125C All 1 mA 25 Mbps, VI= VCCor 0 V, no load 4 VCC2supply current ICC2Quiescent, VI= VCCor 0 V, no load -55C to +125C All 6.5 mA 25 Mbps, VI= VCCor 0 V, no load 7.5 High level output voltage VOHIOH= -4 mA, see figure 4 -55C to +125C All VCC 0.4 V IOH= -20 A, see figure 4 VCC 0.1 Low level

33、 output voltage VOLIOH= 4 mA, see figure 4 -55C to +125C All 0.4 V IOH= 20 A, see figure 4 0.1 Input voltage hysteresis VI(HYS)+25C All 150 typical mV High level input current IIHIN at 2 V -55C to +125C All 10 A Low level input current IILIN at 0.8 V -55C to +125C All -10 A High impedance output cur

34、rent IOZEN , IN at VCC+25C 02 1 typical A Input capacitance to ground CIIN at VCC, VI= 0.4 sin (4E6t) +25C All 1 typical pF Common mode transient immunity CMTI VI= VCCor 0 V, see figure 8 -55C to +125C All 25 kV/s See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or network

35、ing permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08627 REV PAGE 8 TABLE I. Electrical performance characteristics - continued. 1/ Limits Test Symbol Conditions VCC1at 5 V, VCC2at 3.3 V operationTemperature, TA Device ty

36、pe Min Max Unit Propagation delay, low to high level output tPLHEN at 0 V, see figure 4 -55C to +125C 01 3 20 ns Propagation delay, high to low level output tPHLEN at 0 V, see figure 4 -55C to +125C 01 3 20 ns Pulse skew |tPHL tPLH| tsk(p)EN at 0 V, see figure 4 -55C to +125C 01 1 ns Part to part sk

37、ew tsk(pp)2/ -55C to +125C All 5 ns Output signal rise time trEN at 0 V, see figure 4 +25C All 2 typical ns Output signal fall time tfEN at 0 V, see figure 4 +25C All 2 typical ns Sleep mode propagation delay, high level to high impedance output tPHZSee figure 5 +25C 02 11 typical ns Sleep mode prop

38、agation delay, high impedance to high level output tPZHSee figure 5 +25C 02 6 typical s Sleep mode propagation delay, low level to high impedance output tPLZSee figure 6 +25C 02 13 typical ns Sleep mode propagation delay, high impedance to low level output tPZLSee figure 6 +25C 02 6 typical s Failsa

39、fe output delay time from input power loss tfsSee figure 7 +25C All 3 typical s Peak to peak eye pattern jitter tjit(PP) 150 Mbps NRZ data input, see figure 9 +25C All 1 typical ns 150 Mbps unrestricted bit run length data input, see figure 9 2 typical ns See footnotes at end of table. Provided by I

40、HSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08627 REV PAGE 9 TABLE I. Electrical performance characteristics continued. 1/ Limits Test Symbol Conditions VCC1at 3.3 V, VCC2a

41、t 5 V operationTemperature, TADevice type Min Max Unit VCC1supply current ICC1Quiescent, VI= VCCor 0 V, no load -55C to +125C All 0.5 mA 25 Mbps, VI= VCCor 0 V, no load 2 VCC2supply current ICC2Quiescent, VI= VCCor 0 V, no load -55C to +125C All 12 mA 25 Mbps, VI= VCCor 0 V, no load 14 High level ou

42、tput voltage VOHIOH= -4 mA, see figure 4 -55C to +125C All VCC 0.8 V IOH= -20 A, see figure 4 VCC 0.1 Low level output voltage VOLIOH= 4 mA, see figure 4 -55C to +125C All 0.4 V IOH= 20 A, see figure 4 0.1 Input voltage hysteresis VI(HYS)+25C All 150 typical mV High level input current IIHIN at 2 V

43、-55C to +125C All 10 A Low level input current IILIN at 0.8 V -55C to +125C All -10 A High impedance output current IOZEN , IN at VCC+25C 02 1 typical A Input capacitance to ground CIIN at VCC, VI= 0.4 sin (4E6t) +25C All 1 typical pF Common mode transient immunity CMTI VI= VCCor 0 V, see figure 8 -

44、55C to +125C All 25 kV/s See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08627 REV PAGE 10 TABLE I. Electrical performance character

45、istics - continued. 1/ Limits Test Symbol Conditions VCC1at 3.3 V, VCC2at 5 V operationTemperature, TA Device type Min Max Unit Propagation delay, low to high level output tPLHEN at 0 V, see figure 4 -55C to +125C 01 3 21 ns Propagation delay, high to low level output tPHLEN at 0 V, see figure 4 -55

46、C to +125C 01 3 21 ns Pulse skew |tPHL tPLH| tsk(p)EN at 0 V, see figure 4 -55C to +125C 01 1 ns Part to part skew tsk(pp)2/ -55C to +125C All 5 ns Output signal rise time trEN at 0 V, see figure 4 +25C All 1 typical ns Output signal fall time tfEN at 0 V, see figure 4 +25C All 1 typical ns Sleep mo

47、de propagation delay, high level to high impedance output tPHZSee figure 5 +25C 02 9 typical ns Sleep mode propagation delay, high impedance to high level output tPZHSee figure 5 +25C 02 5 typical s Sleep mode propagation delay, low level to high impedance output tPLZSee figure 6 +25C 02 9 typical ns Sleep mode propagation delay, high impedance to low level output tPZLSee figure 6 +25C 02 5 typical s Failsafe output delay time from input power loss tfsSee figure 7 +25C All 3 typical s Peak to peak eye pattern jitter tjit(PP) 150 Mbps NRZ data input, see f