DLA DSCC-VID-V62 08630-2008 MICROCIRCUIT LINEAR SENSOR SIGNAL CONDITIONING DEVICE FOR CLOSED LOOP MAGNETIC CURRENT SENSOR MONOLITHIC SILICON《单片硅闭路磁流传感器用传感器信号调理装置线性微电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-

2、MM-DD CHECKED BY RAJESH PITHADIA APPROVED BY ROBERT M. HEBER TITLE MICROCIRCUIT, LINEAR, SENSOR SIGNAL CONDITIONING DEVICE FOR CLOSED LOOP MAGNETIC CURRENT SENSOR, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/08630 08-08-12 REV PAGE 1 OF 14 AMSC N/A 5962-V056-08 Provided by IHSNot for

3、 ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08630 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance sensor signal conditioning dev

4、ice for closed loop magnetic current sensor microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identif

5、ying the item on the engineering documentation: V62/08630 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 DRV401-EP Sensor signal conditioning device for closed loop magnetic current sensor

6、 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 20 SO-20 Plastic surface mount with thermal pad 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture:

7、Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V6

8、2/08630 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage (VDD) +7 V maximum Signal input terminals: Voltage . -0.5 V to VDD+ 0.5 V 2/ Differential amplifier . -10 V to +10 V 3/ Current at IS1 and IS2 . 75 mA maximum Current (pins other than IS1 and IS2) 25 mA maximum 2/ ICOMPshort circuit

9、. +250 mA 4/ Operating junction temperature (TJ) . +150C Storage temperature range (TSTG) -55C to +150C Electrostatic discharge rating: Human body model (HBM) : Pins IAIN1and IAIN2only . 1 kV All other pins . 4 kV Power dissipation (PD) . 231 mW Thermal resistance, junction to case (JC) . 0.37C/W Th

10、ermal resistance, junction to ambient (JA) 27C/W 1.4 Recommended operating conditions. 5/ Operating free-air temperature range (TA) -55C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional op

11、eration of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Input terminals are diode clamped to the power supply rails. Inp

12、ut signals that can swing more than 0.5 V beyond the supply rails must be limited, except for the differential amplifier input pins. 3/ These inputs are not internally protected against over voltage. The differential amplifier input pins must be limited to 5 mA, maximum or 10 V, maximum. 4/ Power li

13、mited; observe maximum junction temperature. 5/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for Resa

14、leNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08630 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies shou

15、ld be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacture

16、rs name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions a

17、nd electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and f

18、igure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Test circuit. The test circuit shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS,

19、 OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08630 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Limits Test Symbol Conditions 2/Temperature, TA Device type Min Max Unit Differential amplifier RL= 10 k to 2.5 V, VREFIN= 2.5 V Offset voltage section Offset voltage, RTO 3/ VOSGain 4

20、V/V +25C 01 0.1 mV Offset voltage drift, RTO 3/ dVOS/ dT -55C to +125C 01 0.1 typical V / C Offset voltage, RTO 3/ VOSGain 4 V/V -55C to +125C 01 0.17 mV CMRR versus common mode, RTO CMRR -1 V to +6 V, VREF= 2.5 V +25C 01 280 V / V PSRR versus power supply, RTO PSRR VREFnot included +25C 01 50 V / V

21、 Signal input section Common mode voltage range VCM+25C 01 -1 VDD+ 1 V Signal output section Signal over range indication (over range), delay VIN= 1 V step 4/ -55C to +125C 01 2.5 to 3.5 typical s Voltage output swing from negative rail, over range trip level I = +2.5 mA, CMP trip level +25C 01 +85

22、mV Voltage output swing from positive rail, over range trip level I = -2.5 mA, CMP trip level +25C 01 VDD- 85 mV Short circuit current ISCVOUTconnected to GND +25C 01 -18 typical mA VOUTconnected to VDD+20 typical Gain, VOUT/ VIN DIFF-55C to +125C 01 4 typical V/V Gain error +25C 01 0.3 % Gain error

23、 drift -55C to +125C 01 0.1 typical ppm/C Linearity error RL= 1 k +25C 01 10 typical ppm See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO.

24、 V62/08630 REV PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Limits Test Symbol Conditions 2/Temperature, TA Device type Min Max Unit Frequency response section Bandwidth BW -3 dB +25C 01 2 typical MHz Slew rate SR CMVR = -1 V to +4 V +25C 01 6.5 typical V / s Settling time, l

25、arge signal dV 2 V to 1 %, no external filter +25C 01 0.9 typical s Settling time dV 0.4 V to 0.01 % +25C 01 14 typical s Input resistance section Differential +25C 01 16.5 23.5 k Common mode +25C 01 41 59 k External reference input +25C 01 41 59 k Noise section Output voltage noise density, RTO Com

26、pensation loop disabled, f = 1 kHz +25C 01 170 typical nV / Hz Compensation loop section DC stability Probe f = 250 kHz, RLOAD= 20 Offset error 5/ Deviation from 50% PWM, Pin gain = L +25C 01 0.03 typical % Offset error drift 5/ Deviation from 50% PWM, Pin gain = L -55C to +125C 01 7.5 typical ppm/C

27、 Gain, pin gain = L | VICOMP1| - | VICOMP2| +25C 01 -200 200 ppm / V Power supply rejection ratio PSRR Probe loop f = 250 kHz +25C 01 500 typical ppm / V Frequency response section Open loop gain, two modes, 7.8 kHz Pin gain H/L +25C 01 24 typical 32 typical dB See footnotes at end of table. Provide

28、d by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08630 REV PAGE 7 TABLE I. Electrical performance characteristics Continued. 1/ Limits Test Symbol Conditions 2/Temperature

29、, TA Device type Min Max Unit Probe coil loop section Input voltage clamp range Field probe current . See the product data sheet for details regarding the exposed thermal pad dimensions. 4. Falls within reference to JEDEC SO-20. FIGURE 1. Case outline continued. Provided by IHSNot for ResaleNo repro

30、duction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08630 REV PAGE 12 Device type 01 Case outline X (See note) Terminal number Terminal symbol Description 1 PWM Pulse width modulator (PWM) output from pro

31、be circuit (inverted). 2 PWM PWM output from probe circuit. 3 ERROR Error flag: open drain output. 4 DEMAG Control input. 5 GAIN Control input for open loop gain: low = normal, high = -8 dB. 6 REFOUTOutput for internal 2.5 V reference voltage. 7 REFINInput for zero reference to differential amplifie

32、r. 8 VOUTOutput for differential amplifier. 9 IAIN2Noninverting input of differential amplifier. 10 IAIN1Inverting input of differential amplifier. 11 GND2 Ground connection. Connect to GND1. 12 ICOMP2Output 2 of compensation coli driver. 13 ICOMP1Output 1 of compensation coli driver. 14 VDD2Supply

33、voltage. Connect to VDD1. 15 CCdiag Control input for wire break detection: high = enable 16 OVER RANGE Open drain output for over range indication: low = over range. 17 VDD1Supply voltage. 18 IS2 Probe connection 2. 19 GND1 Ground connection. 20 IS1 Probe connection 1. NOTE: Exposed thermal pad on

34、underside, connect to GND1. FIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08630 REV PAGE 13 NOTES: 1. This is a simplified probe

35、interface circuit. The probe is connected between S1 and S2. 2. MOS components function as switches only. FIGURE 3. Test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 162

36、36 DWG NO. V62/08630 REV PAGE 14 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, cl

37、assification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6.

38、NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes wit

39、hout notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing adminis

40、trative control number 1/ 2/ 3/ Device manufacturer CAGE code Part marking Vendor part number V62/08630-01XE 01295 DRV401M DRV401M-EP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ For the most current package and

41、 ordering information, see the package option addendum at the end of the manufacturers data sheet , or use website . 3/ Package drawings, standard packaging quantities, thermal data, symbolization, and printed circuit board (PCB) design guidelines are available at CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-