DLA DSCC-VID-V62 09610-2008 MICROCIRCUIT DIGITAL TRIPLE BUFFER DRIVER WITH OPEN DRAIN OUTPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHE

2、CKED BY RAJESH PITHADIA APPROVED BY ROBERT M. HEBER TITLE MICROCIRCUIT, DIGITAL, TRIPLE BUFFER / DRIVER WITH OPEN DRAIN OUTPUTS, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09610 08-12-03 REV PAGE 1 OF 11 AMSC N/A 5962-V007-09 Provided by IHSNot for ResaleNo reproduction or networkin

3、g permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09610 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance triple buffer / driver with open drain outputs microcircuit, with

4、 an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/09610 - 01

5、 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVC3G07-EP Triple buffer / driver with open drain outputs 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter

6、Number of pins JEDEC PUB 95 Package style X 8 MO-187-CA Plastic surface mount 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash

7、 palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) -0.5 V to 6.5 V Input voltage range (VI) -0.5 V to 6.5 V Voltage range applied to any output in the high impedance or power off state (VO) -0.5 V to 6.5 V 2/ Voltage range applied to any output in the high or low state (V

8、O) -0.5 V to 6.5 V 2/ 3/ Input clamp current (IIK) with VI 0 -50 mA maximum Output clamp current (IOK) with VO 0 -50 mA maximum Continuous output current 50 mA maximum Continuous current through VCCor GND . 100 mA maximum Package thermal impedance (JA) . 227C/W 4/ Storage temperature range (TSTG). -

9、65C to +150C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied

10、. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output negative voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The value of VCCis provided in the recommended operating conditions table. 4/

11、The package thermal impedance is calculated in accordance with JESD 51-7.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09610 REV PAGE 3 1.4 Recommended operating

12、 conditions. 5/ 6/ Supply voltage (VCC): Operating . 1.65 V to 5.5 V Data retention only . 1.5 V minimum High level input voltage (VIH): VCC= 1.65 V to 1.95 V 0.65 V x VCCminimum VCC= 2.3 V to 2.7 V 1.7 V minimum VCC= 3 V to 3.6 V . 2 V minimum VCC= 4.5 V to 5.5 V 0.7 V x VCCminimum Low level input

13、voltage (VIL): VCC= 1.65 V to 1.95 V 0.35 V x VCCmaximum VCC= 2.3 V to 2.7 V 0.7 V maximum VCC= 3 V to 3.6 V . 0.8 V maximum VCC= 4.5 V to 5.5 V 0.3 V x VCCmaximum Input voltage range (VI). 0 V to 5.5 V Output voltage range (VO) 0 V to 5.5 V Low level output current (IOL) : VCC= 1.65 V 4 mA maximum

14、VCC= 2.3 V 8 mA maximum VCC= 3 V . 16 mA maximum 24 mA maximum VCC= 4.5 V 32 mA maximum Input transition rise or fall rate (t / V): VCC= 1.8 V 0.15 V, 2.5 V 0.2 V . 20 ns / V VCC= 3.3 V 0.3 V 10 ns / V VCC= 5 V 0.5 V . 5 ns / V Operating free-air temperature range (TA) . -55C to +125C _ 5/ All unuse

15、d inputs of the device must be held at VCCor GND to ensure proper device operation. 6/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the sta

16、ted limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09610 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconducto

17、r Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.

18、3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum

19、 and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case o

20、utline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Truth table. The truth table shall be as shown in figure 3. 3.5.4 Logic diagram. The logic diagram shall be as shown in figure 4. 3.5.5 Timing waveforms and test

21、circuit. The timing waveforms and test circuit shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09610 REV PAGE 5 TABLE I. Electrical

22、performance characteristics. 1/ Limits Test Symbol ConditionsTemperature, TADevice type Min Max Unit VOLIOL= 100 A, VCC= 1.65 V to 5.5 V -55C to +125C 01 0.1 V Low level output voltage IOL= 4 mA, VCC= 1.65 V 0.45 IOL= 8 mA, VCC= 2.3 V 0.3 IOL= 16 mA, VCC= 3 V 0.4 IOL= 24 mA, VCC= 3 V 0.55 IOL= 32 mA

23、, VCC= 4.5 V 0.55 Input current, A inputs IIVI= 5.5 V or GND, VCC= 0 to 5.5 V -55C to +125C 01 5 A Off current 2/ IoffVIor VO= 5.5 V, VCC= 0 -55C to +125C 01 10 A Supply current ICCVI= 5.5 V or GND, IO= 0 , VCC= 1.65 V to 5.5 V -55C to +125C 01 10 A Delta supply current ICCOne input at VCC 0.6 V, ot

24、her inputs at VCCor GND, VCC= 3 V to 5.5 V -55C to +125C 01 500 A Input capacitance CIVI= VCCor GND, VCC= 3.3 V +25C 01 3.5 typical pF Propagation delay time tPDFrom input A to output Y, VCC= 2.5 V 0.2 V, see figure 5 -55C to +125C 01 0.5 7.3 ns From input A to output Y, VCC= 3.3 V 0.3 V, see figure

25、 5 1.1 6.7 From input A to output Y, VCC= 5 V 0.5 V, see figure 5 0.25 5.9 CpdVCC= 1.8 V, f = 10 MHz +25C 01 3 typical pF Power dissipation capacitance VCC= 2.5 V, f = 10 MHz 3 typical VCC= 3.3 V, f = 10 MHz 4 typical VCC= 5 V, f = 10 MHz 5 typical 1/ Testing and other quality control techniques are

26、 used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is ass

27、ured by characterization and/or design. 2/ This device is fully specified for partial power down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.Provided by IHSNot for ResaleNo reproduction or networking

28、 permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09610 REV PAGE 6 Case X FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLU

29、MBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09610 REV PAGE 7 Case X continued. Dimensions Inches Millimeters Symbol Min Max Min Max A .023 .035 0.60 0.90 A1 .000 .003 0.00 0.10 b .006 .009 0.17 0.25 c .005 NOM 0.13 NOM D .074 .082 1.90 2.10 E .086 .094 2.20 2.40 E1 .118 .125 3.00 3.2

30、0 e .019 BSC 0.50 BSC L .007 .013 0.20 0.35 NOTES: 1. Controlling dimensions are millimeter, inch dimensions are given for reference only. 2. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 mm (0.006 inch) per end. 3. Falls within reference to

31、 JEDEC MO-187-CA. FIGURE 1. Case outlines - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09610 REV PAGE 8 Device type 01 Case outline X Terminal numb

32、er Terminal symbol 1 INPUT 1A 2 OUTPUT 3Y 3 INPUT 2A 4 GND 5 OUTPUT 2Y 6 INPUT 3A 7 OUTPUT 1Y 8 VCCFIGURE 2. Terminal connections. INPUT OUTPUT A Y H H L L FIGURE 3. Truth table. Positive logic FIGURE 4. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without lice

33、nse from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09610 REV PAGE 9 Test S1 tPZL(see notes 2 and 3 ) VLOADtPLZ(see notes 2 and 4 ) VLOADtPHZ/ tPZHVLOADInputs VCCVItr/ tfVMVLOADCLRLV1.8 V 0.15 V VCC 2 ns VCC/ 2 2 x VCC30 pF 1 k 0.15 V 2.5 V 0.20 V

34、VCC 2 ns VCC/ 2 2 x VCC30 pF 500 0.15 V 3.3 V 0.30 V 3 V 2.5 ns 1.5 V 6 V 50 pF 500 0.3 V 5.0 V 0.50V VCC 2.5 ns VCC/ 2 2 x VCC50 pF 500 0.3 V FIGURE 5. Timing waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY

35、 CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09610 REV PAGE 10 Notes: 1. CLincludes probe and jig capacitance. 2. Since this device has open drain outputs, tPLZand tPZLare the same as tpd. 3. tPZLis measured at VM. 4. tPLZis measured at VOL+ V. 5. Waveform 1 is for an out

36、put with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 6. All input pulses are supplied by generators having following character

37、istics: PRR 10 MHz, ZO= 50 . 7. The outputs are measured one at a time with one transaction per measurement. 8. All parameters and waveforms are not applicable to all devices. FIGURE 5. Timing waveforms and test circuit Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted

38、without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09610 REV PAGE 11 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal

39、 documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance wi

40、th the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics

41、of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee

42、 of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ 2/ Device manufacturer CAGE code Package 3/ Top side marking 4/ Vendor part number V62/09610-01XE 01295 Reel of 3000 SOCM SN74LVC3G07MDCUREP 1/ The vendor item drawing estab

43、lishes an administrative control number for identifying the item on the engineering documentation. 2/ For the most current package and ordering information, see the package option addendum at the end of the manufacturers data sheet or use website . 3/ Package drawings, thermal data, and symbolizatio

44、n are available at 4/ The actual top side marking has one additional character that designates the wafer fab/assembly site. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-