DLA DSCC-VID-V62 09624 REV A-2009 MICROCIRCUIT DIGITAL DIGITAL SIGNAL CONTROLLER (DSC) MONOLITHIC SILICON.pdf

1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Correct device 01 and 02 temp range. Phn 12/17/09 T. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV A A A A A A A A A A A A A A A A A A A A A A PAGE 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 REV A A A A A A A A A

2、A A A A A A A A A A A A A PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 REV STATUS OF PAGES REV A A A A A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Origi

3、nal date of drawing CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, DIGITAL SIGNAL CONTROLLER (DSC), MONOLITHIC SILICON YY MM DD 09-11-03 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09624 REV A PAGE 1 OF 61 AMSC N/A 5962-V019-10 .Provided by IHSNot for ResaleNo reproduc

4、tion or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09624 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance digital signal controller microcircuit, with a

5、n operating temperature range of -40C to +125C (device type 02) and an extended operating temperature range of -55C to +125C (device type 01). 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administra

6、tive control number for identifying the item on the engineering documentation: V62/09624 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device type Generic Operating temperature Circuit function 01 SM320F28335-EP -55C to +125

7、C Digital signal controller 02 SM320F28335-EP -40C to +85C Digital signal controller 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 179 Plastic Ball Grid Array Y 176 JEDEC MS-026 Plastic Quad Flatpack 1.2.3 Lead finishes.

8、The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other 1/ Users are cautioned to review the manufacturers data manual for additional user

9、information relating to this device. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09624 REV A PAGE 3 1.3 Absolute maximum ratings. 2/ 3/ Supply voltage range, (

10、VDDIO, VDD3VFL) with respect to VSS. -0.3 V to +4.6 V Supply voltage range, (VDDA2, VDDAIO) with respect to VSSA-0.3 V to +4.6 V Supply voltage range, (VDD) with respect to VSS. -0.3 V to +2.5 V Supply voltage range, (VDD1A18, VDD2A18) with respect to VSSA-0.3 V to +2.5 V Supply voltage range, (VSSA

11、2, VSSAIO, VSS1AGND,VSS2AGND) with respect to VSS. -0.3 V to +0.3V Input voltage range, (VI) . -0.3 V to +4.6 V Output voltage range, (VO) . -0.3 V to +4.6 V Input clamp current, (IIK) (VINVDDIO) 4/ 20 mA Output clamp current, (IOK) (VOVDDIO) 20 mA Operating ambient temperature ranges, (TA): Device

12、type 01 . -55C to +125 5/ Device type 02 -40C to +85C 5/ Junction temperature range, (TJ) -40C to +150C 5/ Storage temperature range, (TSTG) -65C to +150C 5/ 1.4 Recommended operating conditions. 6/ 7/ Device supply voltage, (I/O, VDDIO) . +3.135 V to +3.465 V Device supply voltage CPU, VDD: Device

13、operation 150 MHz . +1.805 V to +1.995 V Device operation 100 MHz . +1.71 V to +1.89 V Supply ground, (VSS, VSSIO, VSSAIO, VSSA2, VSSA1AGND, VSS2AGND) . 0 V ADC supply voltage (3.3 V), (VDDA2, VDDAIO) . +3.135 V to +3.465 V ADC supply voltage, VDD1A18, VDD2A18): Device operation 150 MHz . +1.805 V t

14、o +1.995 V Device operation 100 MHz . +1.71 V to +1.89 V Flash supply voltage, VDD3VFL. +3.135 V to +3.465 V Device clock frequency (system clock), (fSYSCLKOUT) . 2 MHz to 150 MHz High level input voltage, (VIH) . +2 V to VDDIOMaximum low level input voltage, (VIL) . +0.8 V Maximum high level output

15、 source current, VOH= 2.4 V, (IOH): All I/Os except group 2 -4 mA Group 2 7/ -8 mA Maximum low level output sink current, (VOL= VOLMAX, (IOL): All I/Os except group 2 4 mA Group 2 7/ 8 mA Ambient temperature, TA: Device type 01 -55C to +125 Device type 02 -40C to +85C Maximum junction temperature (T

16、J) . +125C _ 2/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied

17、. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3/ All voltage values are with respect to VSS., unless otherwise noted. 4/ Continuous clamp current per pin is 2 mA. This includes the analog inputs which have an internal clamping circuit that clamps

18、 the voltage to a diode drop above VDDA2or below VSSA2. 5/ Long term high temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. 6/ Use of this product beyond the manufacturers design rules or stated parameters is done at

19、 the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 7/ Group 2 pins are as follows: GPIO28, GPIO29, GPIO30, GPIO31, TDO, XCLKOUT, EMU0, EMU1, XINTF pins, GPIO35-87, XRDnullnullnullnullnullnull. Provided by IHSNot for

20、 ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09624 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 High Ef

21、fective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and

22、legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (i

23、f applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are a

24、s specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as specified in figure 3. 3.5.4 Timing waveforms.

25、The timing waveforms shall be as shown in figure 4-39. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09624 REV A PAGE 5 TABLE I. Electrical performance character

26、istics. 1/ Test Symbol Test condition Device type: All 2/ Limits Unit Min Max High level output voltage VOHIOH= IOHMAX 2.4 V IOH= 50 A VDDIO 0.2 Low level output voltage VOLIOL= IOLMAX 0.4 V Input current (low level) Pin with pullup enable IILVDDIO= 3.3 V, VIN= 0 V All I/Os (including XRSnullnullnul

27、lnullnull) -80 -190 A Pin with pulldown enable VDDIO= 3.3 V, VIN= 0 V 2 Input current (high level) Pin with pullup enable IIHVDDIO= 3.3 V, VIN= VDDIO2 A Pin with pulldown enable VDDIO= 3.3 V, VIN= VDDIO28 80 Output current, pullup or pulldown disabled IOZVO= VDDIOor 0 V 2 A Input capacitance CI2 TYP

28、 pF Current consumption by power supply pins at 150 MHz SYSCLOCKOUT Operational (Flash) 3/ IDD The following clocks are enabled: - ePWM1/2/3/4/5/6 - eCAP1/2/3/4/5/6 - eQEP1/2 - eCAN-A - SCI-A/B (FIFO mode) - ADC - SPI-A(FIFO mode) - I2C - CPU Timer 0/1/2 All PWM pins are toggled at 150 kHz. All I/O

29、pins are left unconnected 8/ 315 mA IDDIO4/ 50IDD3VFL 5/ 40 IDDA18 6/ 35IDDA13 7/2 IDLE IDD Flash is powered down. XCLOKOUT is turned off. The following peripheral clocks are enabled: - eCAN-A - SCI-A - SPI-A - I2C 120 mA IDDIO4/ 120 A IDD3VFL 5/ 10 IDDA18 6/ 60IDDA13 7/ 20 STANDBY IDD Flash is powe

30、red down. Peripheral clocks are off. 15 mA IDDIO4/ 120 A IDD3VFL 5/ 10IDDA18 6/ 60 IDDA13 7/ 20HALT IDD Flash is powered down. Peripheral clocks are off. Input clocks is disabled. 10/ 150 TYP 11/ A IDDIO4/ 120 IDD3VFL 5/ 10IDDA18 6/ 60 IDDA13 7/ 20See footnotes at end of table. Provided by IHSNot fo

31、r ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09624 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test condition Device type: All 2/ Limits

32、 Unit Min Max Clocking and Nomenclature (150 MHz devices) On chip oscillator clock tc(OSC), cycle time 28.6 50 ns Frequency 20 35 MHz XCLKIN 12/ tc(CI), cycle time 6.67 250 ns Frequency 4 150 MHz SYSCLKOUTtc(SCO), cycle time 6.67 500 ns Frequency 2 150 MHz XCLKOUT tc(XCO), cycle time 6.67 2000 ns Fr

33、equency 0.5 150 MHz HSPCLK 13/ tc(HCO), cycle time 6.67 ns Frequency 150 MHz LSPCLK 13/ tc(LCO), cycle time 13.3 ns Frequenc 75 MHz ADC clock tc(ADCCLK), cycle time 40 ns Frequency 25 MHz Clocking and Nomenclature (100 MHz devices) On chip oscillator clock tc(OSC), cycle time 28.6 50 ns Frequency 20

34、 35 MHz XCLKIN 14/ tc(CI), cycle time 10 250 ns Frequency 4 100 MHz SYSCLKOUTtc(SCO), cycle time 10 500 ns Frequency 2 100 MHz XCLKOUT tc(XCO), cycle time 10 2000 ns Frequency 0.5 100 MHz HSPCLK 13/ tc(HCO), cycle time 10 ns Frequency 100 MHz LSPCLK 13/ tc(LCO), cycle time 20 ns Frequenc 50 MHz ADC

35、clock tc(ADCCLK), cycle time 40 ns Frequency 25 MHz Input clock frequency Input clock frequency fxResonator (X1/X2) 20 35 MHz Crystal (X1/X2) 20 35 External oscillator/clock source (XCLKIN or X1 pin) 150 MHz device 4 150 100 MHz device 4 100 Limp mode SYSCLKOUT frequency range (with /2 enabled) fl1

36、5 TYP MHz See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09624 REV A PAGE 7 TABLE I. Electrical performance characteristics - Conti

37、nued. 1/ No Test Symbol Test condition Device type: All 2/ Limits Unit Min Max XCLKIN timing requirements PLL enabled C8 Cycle time, XCLKIN tc(CI)See figure 4. 33.3 200 ns C9 Fall time, XCLKIN 15/ tf(CI)6 C10 Rise time, XCLKIN 15/ tr(CI)ns C11 Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)

38、15/ tw(CIL)45 55 % C12 Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)15/ tw(CIH)55XCLKIN timing requirements PLL disabled C8 Cycle time, XCLKIN tc(CI)150 MHz device 6.67 250 ns 100 MHz device 10 250 ns C9 Fall time, XCLKIN 15/ tf(CI)Up to 30 MHz 6 ns 30 MHz to 150 MHz 2 ns C10 Rise time,

39、XCLKIN 15/ tr(CI)Up to 30 MHz 6 ns 30 MHz to 150 MHz 2 ns C11 Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)15/ tw(CIL)45 55 % C12 Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)15/ tw(CIH)45 55 % XCLKOUT switching characteristics (PLL Bypassed or Enabled) 16/ 17/ C1 Cycle time,

40、XCLKOUT tC(XCO)150 MHz device 6.67 ns 100 MHz device 10 C3 Fall time, XCLKOUT tf(XCO)2 TYP ns C4 Rise time, XCLKOUT tr(XCO)2 TYP ns C5 Pull duration, XCLKOUT low tw(XCOL)H-2 H+2 ns C6 Pull duration, XCLKOUT high tw(XCOH)H-2 H+2 ns PLL lock time tp131072tc(OSCCLK)cycles See footnotes at end of table.

41、 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09624 REV A PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test condition Devi

42、ce type: All 2/ Limits Unit Min Max Reset nullnullnullnullnullnullnullnullnulltiming requirements Pulse duration, stable input clock to XRSnullnullnullnullnullhigh tw(RSL1)19/ See figure 5 and 6. 32tc(OSCCLK)cycles Pulse duration, XRSnullnullnullnullnulllow tw(RSL2) Warm reset 32tc(OSCCLK)Pulse dura

43、tion, reset pulse generated by watchdog tw(WDRS)512tc(OSCCLK)TYP Delay time, address/data valid after XRSnullnullnullnullnullhigh td(EX)32tc(OSCCLK)TYP Oscillator start up time tOSCST20/ 1 10 ms Hold time for boot mode pin th(boot-mode)200tc(OSCCLK)cycles GPIO OUTPUT TIMING General Purpose Output sw

44、itching characteristics See figure 8. Rise time, GPIO switching low to high tr(GPO)All GPIOs 8 ns Fall time, GPIO switching high to low tf(GPO)All GPIOs 8 ns Toggling frequency, GPO pins tf(GPO)25 MHz General Purpose Input timing requirements See figure 9 and 10. Sampling period tw(SP) QUALPRD = 0 1

45、tc(SCO)cycles QUALPRD 0 2tc(SCO)* QUALPRD Input qualifier sampling window tw(IQSW)tw(SP) * (n 1) 21/ Pulse duration, GPIO low/high tw(GPI)22/ Synchronous mode 2tc(SCO)With input qualifier tw(IQSW)+ tw(SP) + 1tc(SCO)IDLE mode timing requirements See figure 11. Pulse duration, external wake up signal

46、tw(WAKE-INT)Without input qualifier 2tc(SCO)cycles With input qualifier 5tc(SCO)+ tw(QSW)IDLE mode switching characteristics Delay time, external wake signal to program execution resume 23/ Wake up from flash Flash module in active state td(WAKE-IDLE)Without input qualifier 20tc(SCO)cycles With inpu

47、t qualifier 20tc(SCO)+ tw(IQSW)Wake up from flash Flash module in sleep state Without input qualifier 1050tc(SCO)With input qualifier 1050tc(SCO)+ tw(IQSW) Wake up from SARAM Without input qualifier 20tc(SCO) With input qualifier 20tc(SCO)+ tw(IQSW)STANDBY mode timing requirements tw(WAKE-INT)Withou

48、t input qualifier 3tc(OSCCLK)cycles With input qualifier 24/ (2 + QUALSTDBY) * 3tc(OSCCLK)See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09624 REV A PAGE 9 TABLE I. Electrical performance characteristics - Continued. 1