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本文(DLA DSCC-VID-V62 09636-2011 MICROCIRCUIT DIGITAL LOW VOLTAGE QUAD SPDT CMOS ANALOG SWITCH MONOLITHIC SILICON.pdf)为本站会员(eveningprove235)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA DSCC-VID-V62 09636-2011 MICROCIRCUIT DIGITAL LOW VOLTAGE QUAD SPDT CMOS ANALOG SWITCH MONOLITHIC SILICON.pdf

1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil Original date of d

2、rawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, ,LOW VOLTAGE, QUAD, SPDT, CMOS ANALOG SWITCH, MONOLITHIC SILICON 11-07-14 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09636 REV PAGE 1 OF 13 AMSC N/A 5962-V059-11 Provided by IHSNot for ResaleNo reproductio

3、n or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09636 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low voltage, quad, SPDT, CMOS analog switch microcircuit, wit

4、h an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/09636 - 0

5、1 X B Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 MAX394 Low voltage, quad, SPDT CMOS analog switch 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pin

6、s JEDEC PUB 95 Package style X 20 JEDEC MS012 Small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other P

7、rovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09636 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Voltage referenced to GND: V+ -0.3 V to +17 V V- . +0.3 V to -17 V V+ to V-

8、-0.3 V to +17 V COM_, NO_, NC_, IN_ (V- - 2 V) to (V+ + 2 V) or 30 mA, which ever occurs first 2/ Continuous current, any pin 30 mA Peak current, any pin (pulsed at 1 ms, 10% duty cycle max) 100 mA Continuous power dissipation (TA= +70C) Case X (derate 8.70 mW/C above +70C) 696 mW Operating temperat

9、ure range -55C to +125C Storage temperature range . -65C to 150C Lead temperature (soldering , 10 sec) +300C Electro Static Discharge (ESD) Human Body Model (HBM) 2500 V Class 2 Moisture Sensitive Level (MSL) . Level 1 1.4 Thermal data table. Case outline letter X X Units PC Board Single Layer Multi

10、-Layer 3/ Power dissipation (PD), maximum at +70C 800 1194 mW Power dissipation (PD) derating above +70C 10 14.9mW/C Thermal resistance, junction to case (JC) 20 23 C/W Thermal resistance, junction to ambient (JA) 100 67C/W 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JED

11、EC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10t

12、h Street, Suite 240S, Arlington, VA 22201.) 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended oper

13、ating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2/ Signals on NC, NO, COM, or IN exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3/ Package thermal resistanc

14、es were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to manufacturer data. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AN

15、D MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09636 REV PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESD

16、S identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as speci

17、fied in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal conn

18、ections shall be as shown in figure 2. 3.5.3 Functional diagram. The functional diagram shall be as shown in figure 3. 3.5.4 Switching time test circuit. The switching time and test circuit shall be as shown in figure 4. 3.5.5 Channel capacitance. The channel capacitance shall be as shown in figure

19、5. 3.5.6 Break before make delay. The break before make delay shall be as shown in figure 6. 3.5.7 Charge injection. The charge injection shall be as shown in figure 7. 3.5.8 Off isolation. The off isolation shall be as shown in figure 8. 3.5.9 Cross talk test circuit. The cross test circuit shall b

20、e as shown in figure 9. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09636 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ TALimi

21、ts 3/ Unit Min Max DUAL SUPPLIES Switch Analog signal range VCOM, VNO, VNC4/ 0 V+ V On resistance RONV+ = 4.5 V, V- = -4.5 V, VNCor VNO= 3.5 V, ICOM= 10 mA VINH= 2.4 V, VINL= 0.8 V 25C 30 -55C to 125C 45 On resistance matching between channels 5/ RONVNCor VNO= 3 V, ICOM= 10 mA V+ = 5 V, V- = -5 V 25

22、C 2 -55C to 125C 4 On resistance flatness 5/ RFLAT(ON)VNCor VNO= 3 V, 0 V, -3 V ICOM= 10 Ma, V+ = 5 V, V- = -5 V 25C 4 -55C to 125C 6 NC or NO off leakage current 6/ INC(OFF)or INO(OFF)VCOM = 4.5 V, VNCor VNO= 4.5 V V+ = 5.5 V, V- = -5.5 V 25C -0.1 +0.1 nA -55C to 125C -20 +20 COM leakage current 6/

23、 ICOM(ON)VCOM = 4.5 V, VNCor VNO= 4.5 V V+ = 5.5 V, V- = -5.5 V 25C -0.2 +0.2 nA -55C to 125C -20 +20 Digital logic input Input current with input voltage high IINHVIN= 2.4 V, all others = 0.8 V -1.0 +1.0 A Input current with input voltage low IINLVIN= 0.8 V, all others = 2.4 V -1.0 +1.0 A Logic hig

24、h input voltage VA_H-55C to 125C 2.4 V Logic low input voltage VA_L-55C to 125C 0.8 V Dynamic Turn ON time tONVCOM= 3 V See figure 4 25C 130 ns -55C to 125C 175 Turn OFF time tOFFVCOM= 3 V See figure 4 25C 75 -55C to 125C 100 Break before make time delay 4/ tDSee figure 6 25C 2 ns Charge injection 4

25、/ VCTECL= 1.0 nF, VGEN= 0 V, RGEN= 0 , See figure 7 25C 10 pC Off isolation 7/ VISORL= 50 , CL= 5 pF, f = 1 MHz See figure 5 25C 66 TYP dB Cross talk 8/ VCTRL= 50 , CL= 5 pF, f = 1 MHz See figure 9 25C 88 TYP dB Off capacitance COFFf = 1 MHz, See figure 5 25C 12 TYP pF COM Off capacitance CCOM(OFF)f

26、 = 1 MHz, See figure 5 25C 12 TYP Channel On capacitance CCOM(ON)f = 1 MHz, See figure 5 25C 39 TYP Supply Power supply range 2.4 8 V Positive supply current I+ All channels on or off, V+ = 5.5 V, V- = -5.5 V, VIN= 0 V or V+ -1.0 +1.0 A Negative supply current I- -1.0 +1.0 Provided by IHSNot for Res

27、aleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09636 REV PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 10/ TALimits 3/ Unit Min Max SINGLE +5 V SUPPLY

28、 Switch Analog signal range VCOM, VNO, VNC4/ 0 V+ V On resistance RONV+ = 5.0 V, V- = 0 V, VNCor VNO= 3.5 V, ICOM= 1.0 mA VINH= 2.4 V, VINL= 0.8 V 25C 60 -55C to 125C 75 On resistance match between channels 5/ RONVNCor VNO= 3 V, ICOM= 1.0 mA V+ = 5 V 25C 2 -55C to 125C 4 On resistance flatness 5/ RF

29、LAT(ON)VNCor VNO= 3 V, 2 V, 1 V, ICOM= 1.0 mA, V+ = 5 V, V- = 0 V 25C 6 -55C to 125C 8 NC or NO off leakage current 9/ INC(OFF)or INO(OFF)VCOM = 0 V, VNCor VNO= 4.5 V V+ = 5.5 V, V- = 0 V 25C -0.1 +0.1 nA -55C to 125C -20 +20 COM leakage current 9/ ICOM(ON)VCOM = 4.5 V, VNCor VNO= 4.5 V V+ = 5.5 V,

30、V- = 0 V 25C -0.2 +0.2 nA -55C to 125C -20 +20 Digital logic input Input current with input voltage high IINHVIN= 2.4 V, all others = 0.8 V -1.0 +1.0 A Input current with input voltage low IINLVIN= 0.8 V, all others = 2.4 V -1.0 +1.0 A Dynamic Turn ON time tONVCOM= 3 V See figure 4 25C 250 ns -55C t

31、o 125C 300 Turn OFF time tOFFVCOM= 3 V See figure 4 25C 125 -55C to 125C 175 Break before make time delay 4/ tD25C 5 ns Charge injection 4/ VCTECL= 1.0 nF, VGEN= 0 V, RGEN= 0 , 25C 5 pC Supply Power supply range V+ 2.4 16 V Positive supply current I+ All channels on or off, VIN= 0 V or V+ V+ = 5.5 V

32、, V- = 0 V -1.0 +1.0 A Negative supply current I- -1.0 +1.0 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09636 REV PAGE 7 TABLE I. Electric

33、al performance characteristics - Continued. 1/ Test Symbol Conditions 11/ TALimits 3/ Unit Min Max SINGLE +3.3 V SUPPLY Switch Analog signal range VCOM, VNO, VNC4/ 0 V+ V On resistance RONV+ = 3 V, V- = 0 V, VNCor VNO= 1.5 V, ICOM= 1.0 mA VINH= 2.4 V, VINL= 0.8 V 25C 175 -55C to 125C 250 NC or NO of

34、f leakage current 9/ INC(OFF)or INO(OFF)VCOM = 0 V, VNCor VNO= 3 V V+ = 3.6 V, V- = 0 V 25C -0.1 +0.1 nA -55C to 125C -5.0 +5.0 COM leakage current 9/ ICOM(ON)VCOM = 3 V, VNCor VNO= 3 V V+ = 3.6 V, V- = 0 V 25C -0.2 +0.2 nA -55C to 125C -20 +20 Digital logic input Input current with input voltage hi

35、gh IINHVIN= 2.4 V, all others = 0.8 V -1.0 +1.0 A Input current with input voltage low IINLVIN= 0.8 V, all others = 2.4 V -1.0 +1.0 A Dynamic Turn ON time 4/ tONVCOM= 1.5 V, See figure 4 25C 400 ns Turn OFF time 4/ tOFFVCOM= 1.5 V, See figure 4 25C 150 Break before make time delay 4/ tDSee figure 6

36、25C 5 ns Charge injection 4/ VCTECL= 1.0 nF, VGEN= 0 V, RGEN= 0 , See figure 7 25C 5 pC Supply Power supply range V+ 2.7 16 V Positive supply current I+ All channels on or off, VIN= 0 V or V+ V+ = 3.6 V, V- = 0 V -1.0 +1.0 A Negative supply current I- -1.0 +1.0 1/ Testing and other quality control t

37、echniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product perfo

38、rmance is assured by characterization and/or design. 2/ V+ = 5 V 10%, V- = -5 V 10%, GND = 0 V, VINH= 2.4 V, VINL= 0.8 V, TA= -55C to 125C (unless otherwise noted). 3/ The algebraic convention where the most negative value is a minimum and the most positive value a maximum, is used in this data shee

39、t. 4/ Guaranteed by design. 5/ RON= RON(MAX) RON(MIN). On resistance match between channels and flatness are guaranteed only with specified voltage. Flatness is defined as the difference between the maximum and minimum value of on resistance as measured at the extremes of the specified analog signal

40、 range. 6/ Leakage parameters are 100% tested at the maximum rated hot temperature and guaranteed by correlation at +25C. 7/ See figure 7. Off isolation = 20log10VCOM/VNCor VNO, VCOM= output, VNCor VNO= input to off switch. 8/ Between any two switches. See figure 5 9/ Leakage testing at single suppl

41、y is guaranteed by testing with dual supplies. 10/ V+ = 5 V 10%, V- = -0 V, GND = 0 V, VINH= 2.4 V, VINL= 0.8 V, TA= -55C to 125C (unless otherwise noted). 11/ V+ = 3.0 V to 3.6 V, GND = 0 V, VINH= 2.4 V, VINL= 0.8 V, TA= -55C to 125C (unless otherwise noted). Provided by IHSNot for ResaleNo reprodu

42、ction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09636 REV PAGE 8 Case X Dimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max A .093 .104 2.35 2.65 e .050 BSC 1.27 BSC A1

43、.004 .012 0.10 0.30 E .291 .299 7.40 7.60 b .014 .019 0.35 0.49 E1 .394 .419 10.00 10.65 c .009 .013 0.23 0.32 L .016 .050 0.40 1.27 D .496 .512 12.60 13.00 NOTES: 1. D and E do not include mold flash. 2. Mold flash or protrusions not to exceed 0.15 mm (.006”). 3. Leads to be coplanar within 0.10 mm

44、 (.004”). 4. Meets JEDEC MS012. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09636 REV PAGE 9 Case outline X Device type 01 Terminal number Termin

45、al symbol Terminal number Terminal symbol 1 IN1 11 IN3 2 NO1 12 NO3 3 COM1 13 COM3 4 NC1 14 NC3 5 V- 15 N.C. 6 GND 16 V+ 7 NC2 17 NC48 COM2 18 COM4 9 NO2 19 NO4 10 IN2 20 IN4 N.C. = Not internally connected FIGURE 2. Terminal connections. FIGURE 3. Functional diagram. Provided by IHSNot for ResaleNo

46、 reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09636 REV PAGE 10 FIGURE 4. Switching time test circuit. FIGURE 5. Channel capacitance. Provided by IHSNot for ResaleNo reproduction or networking permitted

47、 without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09636 REV PAGE 11 FIGURE 6. Break before make delay. FIGURE 7. Charge injection. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09636 REV PAGE 12 Frequency Tested Signal generator Analyzer 1 MHz Automatic Synthesizer Tracking spectrum analyz

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