DLA DSCC-VID-V62 10604-2010 MICROCIRCUIT ALL FORMAT OVERSAMPLED COMPONENT VIDEO PC GRAPHICS D A SYSTEM WITH THREE 11 BIT DACs CGMS DATA INSERTION MONOLITHIC SILICON.pdf

1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawi

2、ng CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, ALL FORMAT OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH THREE 11 BIT DACs, CGMS DATA INSERTION, MONOLITHIC SILICON YY MM DD 10-05-25 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/10604 REV PAGE 1 OF 16 AMSC N/A 5962-V05

3、0-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10604 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance All

4、 Format oversampled component Video/PC graphics D/A system with three 11 bit DACs, CGMS data insertion microcircuit, with an operating temperature range of -40C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawin

5、g establishes an administrative control number for identifying the item on the engineering documentation: V62/10604 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device type Generic Circuit function 01 THS8200-EP All Format

6、oversampled component Video/PC graphics D/A system with three 11 bit DACs, CGMS data insertion 1.2.2 Case outline(s). The case outlines shall be as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 80 JEDEC MS-026 Plastic small outline package 1.2.3 Lead finishes. The lead

7、 finishes shall be as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other 1/ Users are cautioned to review the manufacturers data manual for additional user in

8、formation relating to this device. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10604 REV PAGE 3 1.3 Absolute maximum ratings. 2/ Supply voltage range: AVDD to

9、AVSS, VDD_IO to GND_IO . -0.5 V to 4.5 V DVDDto DVSS, VDD_DLL to DVSS . -0.5 to 2.5 V Digital input voltage range to DVSS. -0.5 V to VDD_IO + 0.5 V Operating free air temperature range . -40C to +85C Storage temperature range, (TSTG) . -65C to +150C 1.4 Recommended operating conditions. 3/ Power Sup

10、ply Supply voltage: AVDD3.0 V to 3.6 V DVDD, VDD_DLL 1.65 V to 2.0 V VDD_IO . 1.65 V to 3.6 V Digital and reference inputs High level input voltage, (VIH): VDD_IO = 1.8 V 0.95 V to VDD_IO VDD_IO = 3.3 V 2.3 V to VDD_IO Low level input voltage, (VIL): VDD_IO = 1.8 V DVSSto 0.4 V VDD_IO = 3.3 V DVSSto

11、 1.15 V Clock frequency, (fclk) . 10 MHz to 205 MHz Pulse duration, clock high, (tw(CLKH)40% to 60% Pulse duration, clock low, (tw(CLKL) . 40% to 60% Typical FSADJ resistor, (RFS): VOC= 700 mV 2.99 k VOC= 1 V . 2.08 k 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semicond

12、uctor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown i

13、n 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 2/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the devic

14、e at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 3/ Use of this product beyond the manufacturers design rules or stated parameters is do

15、ne at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE ID

16、ENT NO. 16236 DWG NO. V62/10604 REV PAGE 4 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristi

17、cs are as specified in 1.3, 1.4, 1.5 and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal conne

18、ctions. The terminal connections shall be as shown in figure 2. 3.5.3 Functional overview . The functional overview shall be as shown in figure 3. 3.5.4 Power vs frequency. The power vs frequency shall be as shown in figure 4. 3.5.5 Amplitude vs output frequency. The amplitude vs frequency shall be

19、as shown in figure 5. 3.5.6 Output voltage vs full scale resistance. The output voltage vs full scale resistance shall be as shown in figure 6. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE

20、 IDENT NO. 16236 DWG NO. V62/10604 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test conditions 2/ Limits Unit Min Max Operating analog supply current IAVDDAVDD= 3.3 V, DVDD= 1.8 V VDD_DLL = 1.8 V VDD_IO = 3.3 V, CLK = 80 KHz Video + no bias (700 mV) 98 mA Video + bias

21、(1.05 V) 98 Generic + no bias (1.25 V) 170 AVDD= 3.3 V, DVDD= 1.8 V VDD_DLL = 1.8 V, (DLL by passed) VDD_IO = 1.8 V, CLK = 200 KHz Video + no bias (700 mV) 98 Video + bias (1.05 V) 98 Generic + no bias (1.25 V) 170 Operating digital supply current IDVDDAVDD= 3.3 V, DVDD= 1.8 V VDD_DLL = 1.8 V VDD_IO

22、 = 3.3 V, CLK = 80 KHz Video + no bias (700 mV) 45 mA Video + bias (1.05 V) 45 Generic + no bias (1.25 V) 45 AVDD= 3.3 V, DVDD= 1.8 V VDD_DLL = 1.8 V, (DLL by passed) VDD_IO = 1.8 V, CLK = 200 KHz Video + no bias (700 mV) 95 Video + bias (1.05 V) 95 Generic + no bias (1.25 V) 95 Operating IO supply

23、current IVDD_IO AVDD= 3.3 V, DVDD= 1.8 V VDD_DLL = 1.8 V VDD_IO = 3.3 V, CLK = 80 KHz Video + no bias (700 mV) 2.7 mA Video + bias (1.05 V) 2.7 Generic + no bias (1.25 V) 2.7 AVDD= 3.3 V, DVDD= 1.8 V VDD_DLL = 1.8 V, (DLL by passed) VDD_IO = 1.8 V, CLK = 200 KHz Video + no bias (700 mV) 2.7 Video +

24、bias (1.05 V) 2.7 Generic + no bias (1.25 V) 2.7 Operating DLL supply current IVDD_DLL AVDD= 3.3 V, DVDD= 1.8 V VDD_DLL = 1.8 V VDD_IO = 3.3 V, CLK = 80 KHz Video + no bias (700 mV) 5.6 mA Video + bias (1.05 V) 5.6 Generic + no bias (1.25 V) 5.6 AVDD= 3.3 V, DVDD= 1.8 V VDD_DLL = 1.8 V, (DLL by pass

25、ed) VDD_IO = 1.8 V, CLK = 200 KHz Video + no bias (700 mV) 5.6 Video + bias (1.05 V) 5.6 Generic + no bias (1.25 V) 5.6 Power dissipation PDAVDD= 3.3 V, DVDD= 1.8 V VDD_DLL = 1.8 V VDD_IO = 3.3 V, CLK = 80 KHz Video + no bias (700 mV) 430 mW Video + bias (1.05 V) 430 Generic + no bias (1.25 V) 660 A

26、VDD= 3.3 V, DVDD= 1.8 V VDD_DLL = 1.8 V, (DLL by passed) VDD_IO = 1.8 V, CLK = 200 KHz Video + no bias (700 mV) 500 Video + bias (1.05 V) 500 Generic + no bias (1.25 V) 735 Digital inputs- DC characteristics High level input current IIHVDD_IO = 3.3 V, Digital inputs and CLK at 0 V for IIL; Digital i

27、nputs and CLK at 3.6 V for IIH1 A Low level input current IIL -1 Low level input current, CLK IIL(CLK)1 High level input current, CLK IIH(CLK)-1 Input capacitance CI TA = 25C 5 TYP pF GY, RCr, BCb data inputs setup time ts VDD_IO = 1.8 V 1.5 nA VDD_IO = 3.3 V 1.5 See notes at end of table. Provided

28、by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10604 REV PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 2/ Limits Unit

29、Min Max Digital inputs- DC characteristics - Continued GY, RCr, BCb data inputs hold time tH VDD_IO = 1.8 V 0.5 nA VDD_IO = 3.3 V 0.5 HS_IN, VS_IN, FID inputs setup time ts VDD_IO = 3.3 V 3/ 1.5HS_IN, VS_IN, FID inputs hold time tH VDD_IO = 3.3 V 3/ 0.5Digital process 4/ 10 bit/20 bit $:3:2 with CSM

30、, CSC, 2x interpolation active 73 TYP 5/ pixels 30 bit 4:4:4 33 TYP 5/ VESA clock mode (DLL, CSM, FIRs bypassed) 9 TYP Analog (DAC) outputs DAC resolution 10 6/ bits Integral nonlinearity INL Best fit VDD_IO = 3.3 V, CLK = 500 kHz Video (0.7 + 0.35 V bias) -3 3 LSB Generic (1.25 + 0 V bias) -10 10 D

31、ifferential nonlinearity DNL VDD_IO = 3.3 V, CLK = 500 kHz Video (0.7 + 0.35 V bias) 1/-1 LSB Generic (1.25 + 0 V bias) 1/-1 Power supply ripple rejection ratio of DAC output (full scale) PSRR f = dc to 100 kHz 7/ 42 TYP dB Crosstalk between channels 8/ XTALK CLK = 205 MHz, -1 dB sine wave applied t

32、o active channels, offset bias applied to all channels when turned on, 37. 5 load on all channels 1 MHz sine wave, offset bias off 49 TYP 1 MHz sine wave, offset bias on 42 TYP 10 MHz sine wave, offset bias off 49 TYP 10 MHz sine wave, offset bias on 42 TYP 30 MHz sine wave, offset bias off 48 TYP 3

33、0 MHz sine wave, offset bias on 40.5 TYP Imbalance between DACs KIMBALCLK = 80 MHz 9/ 2% DAC output compliance voltage (video only) VOCRL = 37.5 10/ Video mode (bias offset can be added) 0.72 V Generic mode (bias offset can be added) 1.3 DAC output capacitance (pin capacitance) CO5 TYP pF DAC output

34、 current rise time tri10 to 90% of full scale, CLK = 80 MHz 4.2 ns DAC output current fall time tfi10 to 90% of full scale, CLK = 80 MHz 4.2 Analog output delay tdMeasured from falling edge of CLKIN to 50% of full scale transition 11/ 6.5 TYP Analog output setting time tsaMeasured from 50% of full s

35、cale transition on output to output setting, within 2% 12/ 6.6 TYP Spurious free dynamic range SFDR 1 MHz, -1 dB FS digital sine input -55 TYP dB 10 MHz, -1 dB FS digital sine input -43 TYP Bandwidth (3 dB) BW 90 MHz Glitch energy EglitchFull scale code transition at 205 MSPS 25 pVs See notes at end

36、 of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10604 REV PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ 1/ Testing and other qu

37、ality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing

38、, product performance is assured by characterization and/or design. 2/ Operating free air temperature range; unless otherwise noted. 3/ The HS_IN, VS_IN, and FID input setup/hold times are valid for 3.3 V I/O operation only . These sync inputs are not recommended for use with 1.8 V I/O logic levels.

39、 4/ Defined as the delay on Y pixel data, starting from the rising edge of CLKIN, until the clock period. 5/ CSC contribution: 8 pixels, CSM contribution: 1 pixel, 2x interpolation filter contribution: 18 pixels. 6/ (11 bit internal) 7/ PSRR is defined as 20*log(ripple voltage at DAC output/ripple v

40、oltage at AVDD input). Limits from characterization only. 8/ Crosstalk spec applies to each possible pair of the 3 DAC outputs. Limits from characterization only. 9/ The imbalance between DACs applies to all possible pairs of the three DACs. 10/ Nominal values at RFS= RFS(nom), see Figure 6. Limit f

41、rom characterization only. Excludes bias offset. 11/ This value excludes the digital process delay tD(D). Limit from characterization only. Data is clocked in on the rising edge of CLKIN. 12/ Limit from characterization only. Provided by IHSNot for ResaleNo reproduction or networking permitted witho

42、ut license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10604 REV PAGE 8 Case X Dimensions Symbol Millimeters Symbol Millimeters Min Max Min Max A 1.20 D/E 13.80 14.20 A1 0.95 1.05 D1/E1 11.80 12.20 A2 0.25 TYP D2/E2 9.50 TYP A3 0.05 0.15 e 0.50

43、 BSC b 0.17 0.27 L 0.45 0.75 C 0.13 NOMNotes: 1. This drawing is subject to change without notice. 2. Body dimensions do not include mold flash or protrusion. 3. This package is designed to be soldered to a thermal pad on the board. Refer to manufacturer data for more information. 4. Falls within JE

44、DEC MS-026. FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10604 REV PAGE 9 Case X Terminal number Terminal name Terminal number Terminal

45、 name Terminal number Terminal name Terminal number Terminal name 1 NC 21 BCb9 41 RCr1 61 HS_OUT2 GND_DLL 22 BCb8 42 RCr0 62 VS_OUT 3 CLKIN 23 BCb7 43 HS_IN 63 SDA 4 VDD_DLL 24 BCb6 44 VS_IN 64 SCL 5 I2CA 25 BCb5 45 GND_IO 65 DO9 6 PBKG 26 BCb4 46 VDD_IO 66 DO8 7 FSADJ1 27 BCb3 47 FID 67 DO7 8 FSADJ

46、2 28 BCb2 48 GY9 68 DO6 9 COMP2 29 BCb1 49 GY8 69 DO5 0 COMP1 30 BCb0 50 GY7 70 VDD_IO 11 AVDD 31 DVSS 51 GY6 71 D1CLKO 12 AVSS 32 DVDD 52 GY5 72 GND_IO 13 AGY 33 RCr9 53 GY4 73 DO4 14 AVDD 34 RCr8 54 GY3 74 DO3 15 ABPb 35 RCr7 55 GY2 75 DO2 16 AVSS 36 RCr6 56 GY1 76 DO1 17 ARPr 37 RCr5 57 GY0 77 DO

47、0 18 AVDD 38 RCr4 58 DVSS 78 DVSS 19 VDD_IO 39 RCr3 59 DVDD 79 DVDD 20 GND_IO 40 RCr2 60 RESETB 80 NC NC = Not Connect FIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE

48、 A CODE IDENT NO. 16236 DWG NO. V62/10604 REV PAGE 10 FIGURE 3. Functional overview. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10604 REV PAGE 11 Power for 700 mV DAC output compliance + 350 mV Bias at AVDD = 3.3 V DVDD = 1.8