DLA DSCC-VID-V62 11604 REV A-2010 MICROCIRCUIT DIGITAL VARIABLE RESOLUTION 10-BIT TO 16-BIT R D CONVERTER WITH REFERENCE OSCILLATOR MONOLITHIC SILICON.pdf

1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Original date of drawing YY MM DD CHEC

2、KED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, VARIABLE RESOLUTION, 10-BIT TO 16-BIT R/D CONVERTER WITH REFERENCE OSCILLATOR, MONOLITHIC SILICON 10-12-07 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/11604 REV PAGE 1 OF 14 AMSC N/A 5962-V014-11 Provided by IHSNot for Resale-

3、DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11604 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance variable resolution, 10-bit to 16-bit R/D converter with reference oscillator microcircuit, with an operating te

4、mperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/11604 - 01 X B Drawing Dev

5、ice type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 AD2S1210-EP Variable resolution, 10-bit to 16-bit R/D converter with reference Oscillator 1.2.2 Case outline(s). The case outlines are as specified herein. Outli

6、ne letter Number of pins JEDEC PUB 95 Package style X 48 JEDEC MS026 Low profile Quad Flat Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD Pa

7、lladiumE Gold flash palladium Z Other Provided by IHSNot for Resale-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11604 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Voltage referenced : AVDDto AGND, DGND . -0.3 V to +7.0 V DVDDto AGND, DGND . -0.3 V to +7.0 V VDRIVE

8、to AGND, DGND . -0.3 V to AVDD AGND to DGND . -0.3 V to +0.3 V Analog input voltage to AGND -0.3 V to AVDD+ 0.3 V Digital input voltage to DGND . -0.3 V to VDRIVE+ 0.3 V Digital output voltage to DGND . -0.3 V to VDRIVE+ 0.3 V Analog output voltage swing . -0.3 V to AVDD+ 0.3 V Input current to any

9、pin except supplies 2/ 10 mA Ambient operating temperature range . -55C to +125C Storage temperature range . -65C to +150C Thermal resistance, junction to ambient (JA) 3/ 54C /W Thermal resistance, junction to case (JC) 3/ 15C /W RoHS Compliant temperature, soldering reflow 260(-5/+0) C Electro Stat

10、ic Discharge (ESD) . 2 kV HBM 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) (Applications for copies should be addressed to the Electronic In

11、dustries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1

12、 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteri

13、stics are as specified in 1.3, 1.4, and table I herein. 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “reco

14、mmended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2/ Transient currents of up to 100 mA do not cause latch-up 3/ JEDEC 2S2P standard board (JEDEC 51-2 high-thermal-conductivity (high K) PCB). Provided by IH

15、SNot for Resale-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11604 REV PAGE 4 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be a

16、s shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Functional block diagram. The functional block diagram shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS

17、DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11604 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Test conditions 2/ unless otherwise specified Limits Unit Min Max Sine, Cosine inputs 3/ Voltage amplitude Sinuosoidal waveforms, differential SIN to

18、 SINLO, COS to COSLO 2.3 4.0 Vp-p Input bias current VIN = 4.0 Vp-p, CLKIN = 8.192 MHz 8.25 A Input impedance 485 k Phase lock range Sine/Cosine vs EXC output, Control register D3 = 0 -44 +44 Common mode rejection 20 TYP arc sec/V Angular accuracy 4/ Angular accuracy 7 + 1 LSB arc min Resolution No

19、missing code 10, 12, 14, 16 TYP bits Linearity INL 10-bit 12-bit 14-bit 16-bit 1 2 4 16 LSB Linearity DNL 0.9 LSB Repeatability 1 LSBVelocity output Velocity accuracy 5/ 10-bit 12-bit 14-bit 16-bit Zero acceleration 2 2 4 16 LSB Resolution 6/ 9, 11, 13, 15 TYP bits Dynamic Performance Bandwidth 10-b

20、it 12-bit 14-bit 16-bit CLKIN = 8.192 MHz CLKIN = 8.192 MHz CLKIN = 8.192 MHz CLKIN = 8.192 MHz 2000 2900 900 1200 400 600 100 125 6600 5400 2800 2200 1500 1200 350 275 Hz Tracking rate 10 bit 12-bit 14-bit 16-bit CLKIN = 10.24 MHz CLKIN = 8.192 MHz CLKIN = 10.24 MHz CLKIN = 8.192 MHz CLKIN = 10.24

21、MHz CLKIN = 8.192 MHz CLKIN = 10.24 MHz CLKIN = 8.192 MHz 3125 2500 1250 1000 625 500 156.25 125 rps rps rps rps See footnotes at end of table. Provided by IHSNot for Resale-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11604 REV PAGE 6 TABLE I. Electrical performa

22、nce characteristics - Continued. Test Symbol Test conditions 2/ unless otherwise specified Limits Unit Min Max Dynamic performance Continued. Acceleration Error 10-bit 12-bit 14-bit 16-bit At 50,000 rps 3/, CLKIN = 8.129 MHz At 10,000 rps 3/, CLKIN = 8.129 MHz At 2,500 rps 3/, CLKIN = 8.129 MHz At 1

23、25 rps 3/, CLKIN = 8.129 MHz 30 TYP 30 TYP 30 TYP 30 TYP arc min Setting time 10 step input 10-bit 12-bit 14-bit 16-bit To settle to within 2 LSB, CLKIN = 8.192 MHz To settle to within 2 LSB, CLKIN = 8.192 MHz To settle to within 2 LSB, CLKIN = 8.192 MHz To settle to within 2 LSB, CLKIN = 8.192 MHz

24、0.9 3.3 9.8 48 ms Setting time 179 step input 10-bit 12-bit 14-bit 16-bit To settle to within 2 LSB, CLKIN = 8.192 MHz To settle to within 2 LSB, CLKIN = 8.192 MHz To settle to within 2 LSB, CLKIN = 8.192 MHz To settle to within 2 LSB, CLKIN = 8.192 MHz 2.4 6.1 15.2 68 ms EXC, nullnullnullnullnullnu

25、llnullnullnull, Outputs Voltage Load 100 A, typical differential output (EXC to EXCnullnullnullnullnull) = 7.2 Vp-p 3.2 4.0 Vp-p Center voltage 2.4 2.53 V Frequency 2 20 kHz EXC/EXCnullnullnullnullnullDC Mismatch 30 mV EXC/EXCnullnullnullnullnullAC Mismatch 132 mV THD -58 TYP dB Voltage reference RE

26、FOUT IOUF= 100 A 2.4 2.53 V Drift 100 TYP ppm/C PSRR -60 TYP dB CLKIN, XTALOUT 7/ Voltage input low VIL0.8 V Voltage input high VIH2.0 Logic inputs Voltage input low VILVDRIVER= 2.7 V to 5.25 V VDRIVER= 2.3 V to 2.7 V 0.8 0.7 V Voltage input high VIHVDRIVER= 2.7 V to 5.25 V VDRIVER= 2.3 V to 2.7 V 2

27、0 1.7 Low level input current (Non Pull-Up) IIL10 A Low level input current (Pull-Up) IILRES0, RES1, RDnullnullnullnull, WRnullnullnullnullnull/FSYNCnullnullnullnullnullnullnullnullnull, A0, A1, and RESETnullnullnullnullnullnullnullnullnullpins 80High level input current IIH-10 See footnotes at end

28、 of table. Provided by IHSNot for Resale-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11604 REV PAGE 7 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test conditions 2/ unless otherwise specified Limits Unit Min Max Logic outputs Voltage

29、output low VOLVDRIVER= 2.3 V to 2.7 V 0.4 V Voltage output high VOHVDRIVER= 2.7 V to 5.25 V VDRIVER= 2.3 V to 2.7 V 2.4 2.0 High level three-state leakage IOZH-10 A Low level three-state leakage IOZL10 Power requirements AVDD4.75 5.25 V DVDD4.75 5.25VDRIVE2.3 5.25Power supply IAVDD12 mA IDVDD35IOVDD

30、2 Timing Frequency of clock input fCLKIN6.144 10.24 MHz Clock period (tCK= 1/fCLKIN) tCK98 163 ns A0 and A1 setup time before RDnullnullnullnull/CSnullnullnulllow t1 2 Delay CSnullnullnullfalling edge to WRnullnullnullnullnull/FSYNCnullnullnullnullnullnullnullnullnullrising edge t2 22 Address/data s

31、etup time during a write cycle t33 Address/data hold time during a write cycle t42 Delay WRnullnullnullnullnull/FSYNCnullnullnullnullnullnullnullnullnullrising edge to CSnullnullnullrising edge t5 2 Delay CSnullnullnullrising edge to CSnullnullnullfalling edge t6 10 Delay between writing address and

32、 writing data t72 x tCK+ 20 A0 and A1 hold time after WRnullnullnullnullnull/FSYNCnullnullnullnullnullnullnullnullnullrising edge t8 2 Delay between successive write cycles t96 x tCK+ 20 Delay between rising edge of WRnullnullnullnullnull/FSYNCnullnullnullnullnullnullnullnullnulland falling edge of

33、RDnullnullnullnullt102 Delay CSnullnullnullfalling edge to RDnullnullnullnullfalling edge t11 2 Enable delay RDnullnullnullnulllow to data valid in configuration mode: t12VDRIVE= 4.5 V to 5.25 V VDRIVE= 2.7 V to 3.6 V VDRIVE= 2.3 V to 2.7 V 37 25 30 RDnullnullnullnullrising edge to CSnullnullnullris

34、ing edge t13 2 Disable delay RDnullnullnullnullhigh to data high-Z t14A 16 Disable delay CSnullnullnullhigh to data high-Z t14B 16 Delay between rising edge of RDnullnullnullnulland falling edge of WRnullnullnullnullnull/FSYNCnullnullnullnullnullnullnullnullnullt152 See footnotes at end of table. Pr

35、ovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHSDLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11604 REV PAGE 8 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test conditions 2/ unless otherwise specif

36、ied Limits Unit Min Max Timing - Continued SAMPLEnullnullnullnullnullnullnullnullnullnullnullpulse width t16 2 x tCK + 20 ns Delay from SAMPLEnullnullnullnullnullnullnullnullnullnullnullbefore RDnullnullnullnull/CSnullnullnulllow t17 6 x tCK + 20 Hold time RDnullnullnullnullbefore RDnullnullnullnull

37、low t18 2 Enable delay RDnullnullnullnull/CSnullnullnulllow to data valid t19 VDRIVE = 4.5 V to 5.25 V VDRIVE= 2.7 V to 3.6 V VDRIVE= 2.3 V to 2.7 V 17 21 33 RDnullnullnullnullpulse width t20 6 A0 and A1 set time to data valid when RDnullnullnullnull/CSnullnullnulllow t21 VDRIVE = 4.5 V to 5.25 V VD

38、RIVE= 2.7 V to 3.6 V VDRIVE= 2.3 V to 2.7 V 36 37 29 Delay WRnullnullnullnullnull/FSYNCnullnullnullnullnullnullnullnullnullfalling edge to SCLK rising edge t22 3 Delay WRnullnullnullnullnull/FSYNCnullnullnullnullnullnullnullnullnullfalling edge to SDO release from high-Z t23VDRIVE= 4.5 V to 5.25 V V

39、DRIVE= 2.7 V to 3.6 V VDRIVE= 2.3 V to 2.7 V 16 26 29 Delay SCLK rising edge to DBx valid t24VDRIVE= 4.5 V to 5.25 V VDRIVE= 2.7 V to 3.6 V VDRIVE= 2.3 V to 2.7 V 24 18 32 SCLK high time t250.4 x tCKSCLK low time t260.4 x tCKSDI setup time prior to SCLK falling edge t273 SDI hold time after SCLK fal

40、ling edge t282 Delay WRnullnullnullnullnull/FSYNCnullnullnullnullnullnullnullnullnullrising edge to SDO high-Z t29 15 Delay from SAMPLEnullnullnullnullnullnullnullnullnullnullnullbefore WRnullnullnullnullnull/FSYNCnullnullnullnullnullnullnullnullnullfalling edge t30 6 x tCK + 20 Delay CSnullnullnull

41、falling edge to WRnullnullnullnullnull/FSYNCnullnullnullnullnullnullnullnullnullfalling edge in normal mode t312 A0 and A1 setup time before WRnullnullnullnullnull/FSYNCnullnullnullnullnullnullnullnullnullfalling edge t32 2 A0 and A1 setup time before WRnullnullnullnullnull/FSYNCnullnullnullnullnull

42、nullnullnullnullfalling edge 8/ t33In normal mode, A0 = 0, A1 = 0/1 In configuration mode, A0 = 1, A1 = 1 24 x tCK+ 5 8 x tCK+ 5 Delay WRnullnullnullnullnull/FSYNCnullnullnullnullnullnullnullnullnullrising edge to WRnullnullnullnullnull/FSYNCnullnullnullnullnullnullnullnullnullfalling edge t3410 Fre

43、quency of SCLK input fSCLKVDRIVE= 4.5 V to 5.25 V VDRIVE= 2.7 V to 3.6 V VDRIVE= 2.3 V to 2.7 V 20 25 15 MHz See footnotes at end of table. Provided by IHSNot for Resale-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11604 REV PAGE 9 TABLE I. Electrical performance

44、characteristics - Continued. 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be t

45、ested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ AVDD= DVDD= 5 V 5%, CLKIN = 8.192 MHz 25%, EXC, EXCnullnullnullnullnullfrequency = 10 kHz to 20 kHz (10 bit); 6 kHz to 20 kHz (12 bit); 3 kHz to 12 kHz (14 bit); 2 kHz to 10 kHz

46、 (16 bit); TA= -55C to 125C (unless otherwise noted). 3/ The voltages SIN, SINLO, COS and COSLO, relative to AGND, must always be between 0.15 V and AVDD 0.2 V. 4/ All specifications within the angular accuracy parameter are tested at constant velocity, that is, zero acceleration. 5/ The velocity ac

47、curacy specification includes velocity offset and dynamic ripple. 6/ For example, when RESO = 0 and RES1 = 1, the position output has a resolution of 12 bits. The velocity output has a resolution of 11 bits with the MSB indicating the direct of rotation. In this example, with a CLKIN frequency of 8.

48、192 MHz, the velocity LSB is 0.488 rps, that is 1000 rps (211). 7/ The clock frequency of this device can be supplied with a crystal, an oscillator, or directly from a DSP/microprocessor digital output. When using a signle-ended clock signal directly from the DSP/microprocessor, the XTALOUT pin should remain open circuit and the logic levels outlined under the logic inputs parameters in Table I apply. 8/ A0 and A1 should remain constant for the