DLA DSCC-VID-V62 11605 REV A-2013 MICROCIRCUIT DIGITAL NONVOLATILE MEMORY DUAL 1024-POSITION DIGITAL POTENTIOMETER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Change in Table I for new re-design. - PHN 13-03-12 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Phu H.

2、 Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, NONVOLATILE MEMORY, DUAL 1024-POSITION DIGITAL POTENTIOMETER, MONOLITHIC SILICON 10-12-14 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V6

3、2/11605 REV A PAGE 1 OF 13 AMSC N/A 5962-V054-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11605 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general re

4、quirements of a high performance non volatile memory, dual 1024-position digital potentiometer microcircuit, with an operating temperature range of -40C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing estab

5、lishes an administrative control number for identifying the item on the engineering documentation: V62/11605 - 01 X B Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 AD5235-EP Nonvolatile memory, du

6、al 1024-position digital potentiometer 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 JEDEC MO-153 Small outline Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided b

7、y the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO.

8、 16236 DWG NO. V62/11605 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Voltage referenced : VDDto GND -0.3 V to +7.0 V VSSto GND +0.3 V to -7.0 V VDDto VSS7.0 V VA, VB, VWto GND . VSS 0.3 V to VDD+ 0.3 V Current referenced, IA, IB, IW: Pulsed 2/ 2.5 mA Continuous . 1.1 mA Digital input and output vo

9、ltage to GND -0.3 V to VDD+ 0.3 V Ambient operating temperature range 3/ . -40C to +125C Storage temperature range . -65C to +150C Maximum junction temperature (TJ) 150C Lead temperature, soldering: Vapor phase (60 sec) 215C Infrared (15 sec) 220C Thermal resistance, junction to ambient (JA) . 150C

10、/W Thermal resistance, junction to case (JC) . 28C /W Package power dissipation . (TJ max TA)/ JA2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD22a117 Electrical Erasable programmable ROM (EEPROM) Program/

11、Erase endurance and data retention test. JESD51-2a Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S

12、, Arlington, VA 22201-2107). 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating condition

13、s” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2/ Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A,

14、B and W terminals at a given resistance. 3/ Includes programming of nonvolatile memory. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11605 REV A PAGE 4 3. REQUIREMENTS 3.

15、1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufactu

16、rers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, c

17、onstruction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal functions. The terminal functions shall be as s

18、hown in figure 3. 3.5.3 Functional block diagram. The functional block diagram shall be as shown in figure 4. 3.5.4 Timing diagrams. The timing diagrams shall be as shown in figure 5 and 6. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND

19、 MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11605 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test conditions 2/ unless otherwise specified Limits Unit Min Typ 3/ Max DC characteristic-RHEOSTAT mode (All RDACs) Resistor differential nonlinearity

20、4/ R-DNL RWB-1 +1 LSB Resistor integral nonlinearity 4/ R-INL RWB-2 +2 LSB Nominal resistor tolerance RAB/RABCode = full scale -8 +8 % Resistance temperature coefficient (RAB/RAB)Tx10635 ppm/C Wipe resistance RWIW= 1 V/RWB, VDD= 5 V, code = half scale 30 65 IW= 1 V/RWB, VDD= 3 V, code = half scale 5

21、0 Nominal resistance match RAB1/RAB2Code = full scale, TA = 25C 0.1 % DC characteristics Potentiometer divider mode (All RDACs) Resolution N 10 Bits Differential nonlinearity 5/ DNL -1 +1 LSB Integral nonlinearity 5/ INL -1 +1 LSB Voltage divider temperature coefficient (VW/VW)T x 106Code = half sca

22、le 15 ppm/C Full scale error VWFSECode = full scale -7 0 LSB Zero scale error VWZSECode = zero scale 0 5 LSB Resistor terminals Terminal voltage range 6/ VA, VB, VWVSSVDDV Capacitance Ax, Bx 7/ CA, CBf = 1 MHz, measured to GND, code = half scale 11 pF Capacitance Wx 7/ CW80 Common mode leakage curre

23、nt 7/ 8/ ICMVW= VDD/2 0.01 1 A Digital inputs and outputs Input logic high VIHWith respect to GND, VDD= 5 V 2.4 V Input logic low VILWith respect to GND, VDD= 5 V 0.8 Input logic high VIHWith respect to GND, VDD= 3 V 2.1 Input logic low VILWith respect to GND, VDD= 3 V 0.6 Input logic high VIHWith r

24、espect to GND, VDD= +2.5 V, VSS= -2.5 V 2.0 Input logic low VILWith respect to GND, VDD= +2.5 V, VSS= -2.5 V 0.5 Output logic high (SDO, RDY) VOHRPULL-UP = 2.2 k to 5 V 4.9 Output logic low VOLIOL= 1.6 mA, VLOGIC= 5 V 0.4 Input current IIL2.25 A Input capacitance 7/ CIL5 pF See footnotes at end of t

25、able. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11605 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 2/ unles

26、s otherwise specified Limits Unit Min Typ 3/ Max Power supplies Single supply power range VDDVSS= 0 V 2.7 5.5 V Dual supply power range VDD/VSS2.25 2.75 V Positive supply current IDDVIH= VDDor VIL= GND 2 7 A Negative supply current ISSVIH= VDDor VIL= GND, VDD= +2.5 V, VSS= -2.5 V -6 -2 A EEMEM store

27、 mode current IDD(store)VIH= VDDor VIL= GND, VSS= GND, ISS 0 2 mA ISS(store)VDD= +2.5 V, VSS= -2.5 V -2 mA EEMEM restore mode current 9/ IDD(restore)VIH= VDDor VIL= GND, VSS= GND, ISS 0 320 A ISS(restore)VDD= +2.5 V, VSS= -2.5 V -320 A Power dissipation 10/ PDISSVIH= VDDor VIL= GND 10 40 W Power sup

28、ply sensitivity 7/ PSSVDD= 5 V 10% 0.006 0.01 %/% Dynamic characteristics 7/ 11/ Bandwidth BW -3 dB, VDD/VSS= 2.5 V 125 kHz Total harmonic distortion THDWVA = 1 V rms, VB= 0 V, f = 1 kHz 0.009 % VWsettling time ts VA= VDD, VB= 0 V, VW= 0.50% error band, Code 0x000 to code 0x200 4 s Resistor noise de

29、nsity eN_WBTA = 25C 20 nV/Hz Crosstalk (CW1/CW2) CTVA = VDD, VB= 0 V, measured VW1with VW2making full scale change 30 nV-s Analog crosstalk CTAVDD= VA1 = +2.5 V, VSS= VB1= -2.5 V, measured VW1with VW2= 5 Vp-pf = 1 kHz, Code 1 = 0x200, code 2 = 0x3FF -110 dB See footnotes at end of table. Provided by

30、 IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11605 REV A PAGE 7 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test conditions 2/ unless otherwise specifie

31、d Limits Unit Min Max Interface timing and EEMEM reliability characteristics 12/ Clock cycle time (tCYC) t120 ns CSsetup time t2 10 ns CLK shut down time for CSrise t3 1 tCYC Input clock pulse width t4, t5Clock level high or low 10 ns Data setup time t6From positive CLK transition 5 Data hold time t

32、7From positive CLK transition 5 CSto SDO-SPI line acquire t8 40 CSto SDO-SPI line release t9 50 CLK to SDO propagation delay 13/ t10RP= 2.2 k, CL 20 pF 50 CLK to SDO data hold time t11RP= 2.2 k, CL 20 pF 0 CShigh pulse width 14/ t12 10 CShigh to CShigh 14/ t13 4 tCYC RDY rise to CSfall t14 0 ns CSri

33、se to RDY fall time t15 0.15 0.3 ms Store EEMEM time 15/ 16/ t16Applies to instruction 0x2, 0x3 15 50 ms Read EEMEM time 15/ t16Applies to instruction 0x8, 0x9, and 0x10 7 30 s CSrise to clock rise/Fall setup t17 15 ns Preset pulse width (Asynchronous) 17/ tPRW50 ns Preset response time to wiper set

34、ting 17/ tPRESPPRpulsed low to refresh wiper positions 30 s Power ON EEMEM restore time 17/ tEEMEM30 s Flash/EE memory reliability Endurance 18/ TA = 25C 1 MCycles 100 kCycles Data retention 19/ 100 Years See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permi

35、tted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11605 REV A PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product per

36、formance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ VDD= 3 V to 5.5

37、 V, VSS=0; VDD= 2.5 V, VSS= -2.5 V, VA= VDD, VB= VSS, -40C TA 125C (unless otherwise noted). The part can be operated at 2.7 V single supply, except from 0C to -40C, where a minimum of 3 V is needed. 3/ Typicals (TYP) represent average readings at 25C and VDD= 5V. 4/ Resistor position nonlinearity e

38、rror (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. IW 50 A for VDD= 2.7 V and IW 400 A for VDD= 5 V. 5/ INL and DNL are measured at

39、VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA= VDDand VB= VSS. DNL specification limits of 1 LSB maximum guaranteed monotonic operating conditions. 6/ Resistor terminal A, Resistor terminal B, and resistor terminal W has no limitations on polarity with re

40、spect to each other. Dual supply operation enables ground-referenced bipolar signal adjustment. 7/ Guaranteed by design and not subject to production test. 8/ Common mode leakage current is a measure of the dc leakage from any terminal A, terminal B, or terminal W to a common mode bias level of VDD/

41、2. 9/ EEMEM response mode current is not continuous. Current is consumed while EEMEM locations are read and transferred to the RDAC register. To minimize power dissipation, on a NOP, instruction 0 (0x0) should be issued immediately after instruction 1 (0x1). 10/ PDISSis calculated from (IDDx VDD) +

42、(ISSx VSS). 11/ All dynamic characteristics use VDD= +2.5 V and VSS= -2.5 V. 12/ Guaranteed by design and not subject to production test. See the timing diagrams section for the location of measured values. All input control voltages are specified with tR= tF= 2.5 ns (10% to 90% of 3 V) and timed fr

43、om a voltage level 0f 1.5 V. Switching characteristics are measured using both VDD= 3 V and VDD= 5 V. 13/ Propagation delay depends on the value of VDD, RPULL-UP, and CL. 14/ Valid for commands that do not activate the RDY pin. 15/ RDY pin low only for Instruction 2, Instruction 3, Instruction 8, In

44、struction 9, Instruction 10, and the PRhardware pulse; CMD_8 20 s; CMD_9, CMD_10 7 s; CMD_2, CMD_3 15 ms; PRhardware pulse 30 s. 16/ Store EEMEM time depends on the temperature and EEMEJM writes cycles. Higher timing is expected at a lower temperature and higher write cycles. 17/ Not shown in FIGURE

45、 5 and FIGURE 6. 18/ Endurance is qualified to 100,000 cycles per JEDEC standard 22, method A117 and measured at -40C, +25C, and +125C. 19/ Retention life time equivalent at junction temperature (TJ) = 85C per JEDEC standard 22, method A117. Retention lifetime based on an activation energy of 1 eV d

46、erates with junction temperature in the Flash/EE memory. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11605 REV A PAGE 9 Case X Dimensions Symbol Millimeters Symbol Milli

47、meters Min Max Min Max A 1.20 E 4.30 4.50 A1 0.05 0.15 E1 6.40 TYP b 0.19 0.30 e 0.65 BSC c 0.09 0.20 L 0.45 0.75 D 4.90 5.10 FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11605 REV A PAGE 10 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 CLK 16 RDY 2 SDI 15 CS3 SDO 14 PR4 GND 13 WP5 VSS12 VDD6 A1 11 A2 7 W1 10 W2 8 B1 9 B2 FIGURE 2. Te