DLA DSCC-VID-V62 11608-2011 MICROCIRCUIT DIGITAL CMOS V +5V 4 O SINGLE SPDT SWITCH MONOLITHIC SILICON.pdf

1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Original date of drawing YY MM DD CHECKED BY

2、 Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, CMOS, % V/ +5V , 4 , SINGLE SPDT SWITCH, MONOLITHIC SILICON 11-01-19 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/11608 REV PAGE 1 OF 12 AMSC N/A 5962-V029-11 Provided by IHSNot for ResaleNo reproduction or networking permitted witho

3、ut license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11608 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance CMOS, 5 V/ +5 V, 4 , single SPDT switch microcircuit, with an operating temperature range of

4、 -40C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer,s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/11608 - 01 X E Drawing Device type Case out

5、line Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 ADG619-EP CMOS, 5 V/ +5 V, 4 , single SPDT switch 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 8 J

6、EDEC MO-178 Small outline Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for Resa

7、leNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11608 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Voltage referenced : VDDto VSS13.0 V VDDto GND -0.3 V to +6.5 V VSSto GND +0.3 V to -6.5 V Analog inpu

8、t 2/ VSS 0.3 V to VDD+ 0.3 V Digital input 2/ -0.3 V to VDD+ 0.3 V or 30 mA (which ever occurs first) Peak current, S or D 100 MA (pulsed at 1 ms, 10% duty cycle mzximum) Continuous current, S or D 50 mA Ambient operating temperature range -55C to +125C Storage temperature range . -65C to +150C Maxi

9、mum junction temperature (TJ) 150C Thermal impedance: JA229C /W JC91.99C /W Lead soldering: Reflow, peak temperature . 260(+0/-5)C Time at peak temperature . 20 sec to 40 sec 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies shou

10、ld be addressed to the Electronic Industries Alliance, 3103 North 10thSt., Suite 240-S, Arlington, VA 22201-2107 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. M

11、anufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating co

12、nditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other

13、 conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2/ Overvoltage at IN, S or D are clamped by internal diodes. Current should be limited to the maximum ratings

14、given. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11608 REV PAGE 4 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions a

15、re as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Functional block diagram. The functional block diagram shall be as shown in figure 3. 3.5.4 Tr

16、uth table. The truth table shall be as shown in figure 4. 3.5.5 On Resistance. The On resistance shall be as shown in figure 5. 3.5.6 Off Leakage. The Off leakage shall be as shown in figure 6. 3.5.7 On Leakage . The On leakage shall be as shown in figure 7. 3.5.8 Switching times. The switching time

17、s shall be as shown in figure 8. 3.5.9 Break before making time delay. The break before making time delay shall be as shown in figure 9. 3.5.10 Charge injection. The charge injection shall be as shown in figure 10. 3.5.11 Off isolation. The Off isolation shall be as shown in figure 11. 3.5.12 Channe

18、l to channel crosstalk. The channel to channel crosstalk shall be as shown in figure 12. 3.5.13 Bandwidth. The bandwidth shall be as shown in figure 13. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE

19、IDENT NO. 16236 DWG NO. V62/11608 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test conditions 2/ unless otherwise specified Limits Unit TA= 25C -55C TA +125CMin Max Min Max DUAL SUPPLY Analog switch Analog signal range VDD= +4.5 V, VSS= -4.5 V VSSVDDV On resistance RON

20、VS= 4.5 V, IDS= -10 mA See figure 5 6.5 10 RONMatch between channels RONVS= 4.5 V, IDS= -10 mA 1.1 1.45 On resistance flatness RFLAT (ON)VS= 3.3 V, IDS= -10 mA 1.35 1.6 Leakage currents (VDD= +5.5 V, VSS= -5.5 V) Source off leakage, IS(Off) VS= 4.5 V, VD= 4.5 V, See figure 6 0.25 3 nA Channel On lea

21、kage, ID, IS(On) VS= VD= 4.5 V, See figure 7 0.25 25 Digital inputs Input high voltage VINH2.4 V Input low voltage VINL0.8 Input current, INLor INHVIN = VINLor VINH0.05 TYP 0.1 A Digital input capacitance CIN2 TYP pF Dynamic characteristic 3/ tONRL= 300 , CL= 35 pF, VS= 3.3 V, See figure 8 220 390 n

22、s tOFF75 135Break before make time delay tBBMRL= 300 , CL= 35 pF, VS1= VS2= 3.3 V, See figure 9 70 TYP 10 Charge injection VS-= 0 V, RS= 0 , CL= 1 nF, See figure 10 6 TYP pC Off isolation RL= 50 , CL= 5 pF, f = 1 MHz, See figure 11 - 67 TYP dB Channel to channel crosstalk RL= 50 , CL= 5 pF, f = 1 MH

23、z, See figure 12 - 67 TYP Bandwidth -3 dB RL= 50 , CL= 5 pF, See figure 13 190 TYP MHz CS(Off) f = 1 MHz 25 TYP pF CD, CS(On) 95 TYP Power requirements (VDD= +5.5 V, VSS= -5.5 V) IDDDigital inputs = 0 V or 5.5 V 0.001 TYP 1.0 A ISS0.001 T 1.0See footnotes at end of table. Provided by IHSNot for Resa

24、leNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11608 REV PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Test conditions 2/ unless otherwise specified Limits Unit TA=

25、 25C -55C TA +125CMin Max Min Max SINGLE SUPPLY Analog switch Analog signal range VDD= +4.5 V, VSS= -0 V 0 VDDV On resistance RONVS= 0 V to 4.5 V, IDS= -10 mA See figure 5 10 14 RONMatch between channels RONVS= 0 V to 4.5 V, IDS= -10 mA 1.1 1.4 On resistance flatness RFLAT (ON)VS=1.5 V to 3.3 V, IDS

26、= -10 mA 0.5 TYP 1.4 Leakage currents (VDD= +5.5 V) Source off leakage, IS(Off) VS= 1 V/4.5 V, VD= 4.5 V/1 V, See figure 6 0.25 3 nA Channel On leakage, ID, IS(On) VS= VD= 4.5 V, See figure 7 0.25 25 Digital inputs Input high voltage VINH2.4 V Input low voltage VINL0.8 Input current, INLor INHVIN =

27、VINLor VINH0.05 TYP 0.1 A Digital input capacitance CIN2 TYP pF Dynamic characteristic 3/ tONRL= 300 , CL= 35 pF, VS= 3.3 V, See figure 8 120 215 ns tOFF75 105Break before make time delay tBBMRL= 300 , CL= 35 pF, VS1= VS2= 3.3 V, See figure 9 40 TYP 10 Charge injection VS-= 0 V, RS= 0 , CL= 1 nF, Se

28、e figure 10 110 TYP pC Off isolation RL= 50 , CL= 5 pF, f = 1 MHz, See figure 11 - 67 TYP dB Channel to channel crosstalk RL= 50 , CL= 5 pF, f = 1 MHz, See figure 12 - 67 TYP Bandwidth -3 dB RL= 50 , CL= 5 pF, See figure 13 190 TYP MHz CS(Off) f = 1 MHz 25 TYP pF CD, CS(On) 95 TYP Power requirements

29、 (VDD= +5.5 V) IDDDigital inputs = 0 V or 5.5 V 0.001 TYP 1.0 A 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all

30、parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ VDD= 5 V 10%, VSS= 0 V, GND = 0 V, -55C TA 125C, unless otherwise noted. 3/ Guaranteed by design, not subject to production test. Provided by

31、IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11608 REV PAGE 7 Case X Dimensions Symbol Millimeters Symbol Millimeters Min Max Min Max A 0.90 1.30 E 1.50 1.70 A1 0.05 0.15 E1 2.60 3.0

32、0 A2 0.95 1.45 e 0.65 BSC b 0.22 0.38 L 0.30 0.60 c 0.08 0.22 L1 0.60 BSC D 2.80 3.00 FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11608 REV PAGE

33、8 Case outline X Pin No. Mnemonic Description 1 D Drain terminal. Can be an input or output 2 S1 Source terminal. Can be an input or output 3 GND Ground (0 V) reference. 4 VDDMost positive power supply 5 NC No connect. Not internal connected. 6 IN Logic control input 7 VSSMost negative power supply.

34、 This pin is only used in dual supply applications and should be tied to ground in single supply applications. 8 S2 Source terminal. can be an input or output FIGURE 2. Terminal connections. FIGURE 3. Functional block diagram. IN Switch S1 Switch S2 0 On Off1 Off On FIGURE 4. Truth table. Provided b

35、y IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11608 REV PAGE 9 FIGURE 5. ON Resistance. FIGURE 6. OFF leakage. FIGURE 7. ON Leakage. FIGURE 8. Switching times. FIGURE 9. Break befor

36、e make time delay. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11608 REV PAGE 10 FIGURE 10. Charge injection. FIGURE 11. Off isolation. Provided by IHSNot for ResaleNo r

37、eproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11608 REV PAGE 11 FIGURE 12. Channel to channel crosstalk. FIGURE 13. Bandwidth. Provided by IHSNot for ResaleNo reproduction or networking permitted without

38、license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11608 REV PAGE 12 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Su

39、ch procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacture

40、rs standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manu

41、facturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or con

42、tinued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number V62/11608-01XE 24355 ADG619SRJZ-EP-RL7 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 24355 Analog Devices Rt 1 Industrial Park PO Box 9106 Norwood, MA 02062 Point of contact: 7910 Triad Center Drive Greensboro, NC 27409-9605 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-