DLA DSCC-VID-V62 11617 REV B-2012 MICROCIRCUIT FLOATNG POINT DIGITAL SIGNAL PROCESSOR MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE 40 41 42 43 44 45 46 REV PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Ph

2、u H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, FLOATNG POINT DIGITAL SIGNAL PROCESSOR, MONOLITHIC SILICON 12-03-22 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/11

3、617 REV PAGE 1 OF 46 AMSC N/A 5962-V039-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11617 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requiremen

4、ts of a high performance floating point digital signal processor microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative contr

5、ol number for identifying the item on the engineering documentation: V62/11617 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SM320C6727B-EP Floating point digital signal processor 1.2.2 C

6、ase outline(s). The case outlines are as specified herein. Outline letter Number of pins Package style X 256 Plastic ball grid array 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder di

7、p B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range, CVDD, OSCVDD. -0.3 V to 1.8 V 3/ Supply voltage range, DVDD, PLLHV -0.3 V to 4.0 V Input voltage range: All pins except OSCIN -0.3 V to DVDD+ 0.5 V OSCIN pin . -3.0 V

8、to CVDD+ 0.5 V Output voltage range: All pins except OSCOUT . -0.3 V to DVDD+ 0.5 V OSCOUT pin . -3.0 V to CVDD+ 0.5 V Clamp current . 20 mA Operating case temperature range, (TC) -55C to 125C Storage temperature range (Tstg) -65C to 150C 1/ Stresses beyond those listed under “absolute maximum ratin

9、gs” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may

10、affect device reliability. 2/ All voltage values are with referenced to VSS unless otherwise specified. 3/ If OSCVDDand OSCVSSpins are used as filter pins for reduced oscillator jitter, they should not be connected to CVDDand VSSexternally. Provided by IHSNot for ResaleNo reproduction or networking

11、permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11617 REV PAGE 3 1.3 Recommended operating conditions. 4/ Core supply voltage, (CVDD) . 1.14 V to 1.32 V I/O supply voltage, (DVDD): 3.13 V to 3.47 V Operating free air temperature, (T

12、C) . -55C to 125C Allowed PLL operating conditions Parameter Default Value Allowed Setting or Range Min Max 1 PLLRST = 1 assertion time during initialization N/A 125 ns 2 Lock time before setting PLLEN = 1. After changing D0, PLLM, or input clock N/A 187.5 s 3 PLL input frequency (PLLREF after D0) 5

13、/ 12 MHz 50 MHz 4 PLL multiplier values (PLLM) x13 x4 x25 5 PLL output frequency (PLLOUT before dividers D1, D2, D3) 6/ N/A 140 MHz 600 MHz 6 SYSCLK1 frequency (set by PPLM and dividers D0, D1) PLLOUT/1 divide frequency specification 7 SYSCLK2 frequency (set by PPLM and dividers D0, D2) PLLOUT/2 /2,

14、 /3, or /4 of SYSCLK1 8 SYSCLK3 frequency (set by PPLM and dividers D0, D3) PLLOUT/3 EMIF frequency specification Thermal characteristics for case X _ 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor main

15、tain no responsibility or liability for product used beyond the stated limits. 5/ Some values for the D0 divider produce results outside of this range and should not be selected. 6/ In general, selecting the PLL output clock rate closest to the maximum frequency will decrease clock jitter. 7/ EIA/JE

16、SD51-9 PCB No. Symbol C/W Air Flow (m/s) Two Signal, Two Plane, 101.5 x 114.5 x 1.6 mm, 2 oz Cu. 7/ 1 Thermal resistance junction to ambient RJA25 0 2 Thermal resistance junction to board RJB14.5 0 3 Thermal resistance junction to top of case RJC10 0 4 Thermal metric junction to board JB14 0 5 Therm

17、al metric junction to top of case JT0.39 0 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11617 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

18、(JEDEC) JESD51-9 Test Board for Area Array Surface Mount Packages. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanentl

19、y and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A an

20、d C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions

21、 are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Functional block diagram. The functional block diagram shall be as shown in figure 3. 3.5.4

22、Test and timing diagram. The test and timing diagram shall be as shown in figures 4 to 37. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11617 REV PAGE 5 TABLE I. Electric

23、al performance characteristics. 1/ Test Symbol Conditions 2/ Limits Unit Min Max High level output voltage VOHIO= -100 A DVDD 0.2 V Low level output voltage VOLIO= -100 A 0.2 V High level output current IOHVO= 0.8 DVDD-8 mA Low level output current IOLVO= 0.22 DVDD8 mA High level input current VIH2

24、DVDDV Low level input current VIL0 0.8 V Input hysteresis VHYS0.13 DVDD TYPV Input current and off state output current II, IOZPins without pullup or pulldown 10 A Pins with internal pullup -50 -170 Pins with internal pulldown 50 170 Input transition time ttr25 ns Input capacitance CI7 pF Output cap

25、acitance CO7 pF CVDDSupply 3/ IDD2VCapacitance = 7 pF, CVDD= 1.2 V 658 CPU clock = 250 MHz 555 TYP mA DVDDSupply 3/ IDD3VDVDD = 3.3 V, 32 bit EMIF speed = 100 MHz 58 TYP mA See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,

26、-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11617 REV PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ No Test Symbol Conditions 2/ Limits Unit Min Max EMIF ELECTRICAL DATA/TIMING (See Figure 7 13) EMIF SDRAM interface timing requirements 19 Inpu

27、t setup time, read data valid on D31:0 before EM_CLK rising tsu(EM_DV-EM_CLKH)3 ns 20 Input hold time, read data valid on D31:0 after EM_CLK rising th(EM_CLKHJ-EM_DIV)1.9 EMIF SDRAM interface switching characteristics 1 Cycle time, EMIF clock EM_CLK tc(EM_CLK)10 ns 2 Pulse width, EMIF clock EM_CLK h

28、igh or low tw(EM_CLK)3 3 Delay time, EM_CLK rising to EM_CS0valid td(EM_CLKH-EM_CSV)S7.7 4 Output hold time, EM_CLK rising to EM_CS0invalid toh(EMCLKH-EM_CSIV)S1.15 5 Delay time, EM_CLK rising to EM_WE_DQM3:0 valid td(EM_CLKH-EM_WE-DQMV)S7.7 6 Output hold time, EM_CLK rising to EM_WE_DQM3:0 invalid

29、toh(EM_CLKH-EM_WE-DQMiV)S1.15 7 Delay time, EM_CLK rising to EM_A12:0 and EM_BA1:0 valid td(EM_CLKH-EM_AV)S7.7 8 Output hold time, EM_CLK rising to EM_A12:0 and EM_BA1:0 invalid toh(EMCLKH-EM_AIV)S1.15 9 Delay time, EM_CLK rising to EM_D31:0 valid td(EM_CLKH-EM_DV)S7.7 10 Output hold time, EM_CLK ri

30、sing to EM_D31:0 invalid toh(EMCLKH-EM_DIV)S1.15 11 Delay time, EM_CLK rising to EM_RASvalid td(EM_CLKH-EM_RASV)S7.7 12 Output hold time, EM_CLK rising to EM_RASinvalid toh(EMCLKH-EM_RASIV)S1.15 13 Delay time, EM_CLK rising to EM_CASvalid td(EM_CLKH-EM_CASV)S7.7 14 Output hold time, EM_CLK rising to

31、 EM_CASinvalid toh(EMCLKH-EM_CASIV)S1.15 15 Delay time, EM_CLK rising to EM_WEvalid td(EM_CLKH-EM_WEV)S7.7 16 Output hold time, EM_CLK rising to EM_WEinvalid toh(EMCLKH-EM_WEIV)S1.15 17 Delay time, EM_CLK rising to EM_D31:0 3-stated td(EM_CLKH-EM_DHZ)S7.7 18 Output hold time, EM_CLK rising to EM_D31

32、:0 driving toh(EMCLKH-EM_DLZ)S1.15 EMIF asynchronous interface timing requirements 4/ 5/ 28 Input setup time, read data valid on EM_D31:0 before EM_CLK rising tsu(EM_DV-EM_CLKH)A5 ns 29 Input hold time, read data valid on EM_D31:0 after EM_CLK rising th(EM_CLK-EM_DIV)A2 30 Setup time, EM_WAIT valid

33、before EM_CLK rising edge tsu(EM_CLK-EM_WAITV)A5 31 Hold time, EM_WAIT valid after EM_CLK rising edge th(EM_CLK-EM_WAITIV)A0 33 Pulse width of EM_WAIT assertion and deassertion tw(EM_WAIT)A2E+5 34 Delay from EM_WAIT sampled deasserted on EM_CLK rising to beginning of HOLD phase td(EM_WAITD-HOLD)A4E

34、6/ 35 Setup before end of STROBE phase (if no extended wait state are inserted) by which EM_WAIT must be sampled asserted on EM_CLK rising in order to add extended wait states. 7/ tsu(EM_WAITA-HOLD)A4E 6/ See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permit

35、ted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11617 REV PAGE 7 TABLE I. Electrical performance characteristics Continued. 1/ No Test Symbol Conditions 2/ Limits Unit Min Max EMIF ELECTRICAL DATA/TIMING Continued. (See Figure 7 13) EMIF

36、asynchronous interface switching characteristics 5/ 1 Cycle time, EMIF clock EM_CLK tc(EM_CLK)10 ns 2 Pulse width, high or low, EMIF clock EM_CLK tw(EM_CLK)3 17 Delay time, EM_CLK rising to EM_D31:0 3-stated tdis(EM_CLKH-EM_DHZ)S7.7 18 Output hold time, EM_CLK rising to EM_D31:0 driving tena(EM_CLKH

37、-EM_DLZ)S1.15 21 Delay time, from EM_CLK rising edge to EM_CS2td(EM_CLK-EM_CS2V)A0 8 22 Delay time, EM_CLK rising to EM_WE_DQM3:0 valid td(EM_CLK-EM_WE_DQMV)A0 8 23 Delay time, EM_CLK rising to EM_A12:0 and EM_BA1:0 valid td(EM_CLK-EM_AV)A0 8 24 Delay time, EM_CLK rising to EM_D31:0 valid td(EM_CLK-

38、EM_DV)A0 8 25 Delay time, EM_CLK rising to EM_OEvalid td(EM_CLK-EM_OEV)A0 8 26 Delay time, EM_CLK rising to EM_RWvalid td(EM_CLK-EM_RW)A0 8 27 Delay time, EM_CLK rising to EM_D31:0 3-stated td(EM_CLK-EM_DDIS)A0 8 32 Delay time, EM_CLK rising to EM_WEvalid td(EM_CLK-EM_WE)A0 8 UHPI ELECTRICAL DATA/TI

39、MING (See Figure 14 21) UHPI read and write timing requirements 8/ 9/ 9 Setup time, UHPI_HASlow before DS falling edge tsu(HASL_DSL)5 ns 10 Hold time, UHPI_HASlow after DS falling edge th(DSL_HASL)2 11 Setup time, HAD valid before UHPI_HASfalling edge tsu(HAD_HASL)5 12 Hold time, HAD valid after UHP

40、I_HASfalling edge th(HASL_HAD)5 13 Pulse duration, DS low tw(DSL)15 14 Pulse duration, DS high tw(DSH)2P 15 Setup time, HAD valid before DS falling edge tsu(HAD-DSL)5 16 Hold time, HAD valid after DS falling edge th(DSL-HAD)5 17 Setup time, HD valid before DS rising edge tsu(HD-DSH)5 18 Hold time, H

41、D valid after DS rising edge th(DSH-HD)0 37 Setup time, UHPI_HCSlow before DS falling edge tsu(HCSL-DSL)0 38 Hold time, DS low after UHPI_HCSrising edge th(HRDYH-DSL)1 See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA

42、LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11617 REV PAGE 8 TABLE I. Electrical performance characteristics Continued. 1/ No Test Symbol Conditions 2/ Limits Unit Min Max UHPI ELECTRICAL DATA/TIMING Continued. (See Figure 14 21) UHPI read and write switching characteris

43、tics 9/ 10/ 1 Delay time, DS low to HD valid td(DSL-HDV)Case 1. HPIC or HPIA read 1 15 ns Case 2. HPID read with no auto increment 9*2H+20 11/ Case 3. HPID read with auto increment and read FIFO initially empty 9*2H+20 11/ Case 4. HPID read with auto increment and data previously prefetched into the

44、 read FIFO 1 15 2 Disable time, HD high impedance from DS high tdis(DSH-HDV)1 4 3 Enable time, HD driven from DS low ten(DSL-HDD)3 15 4 Delay time, DS low to UHPI_HRDYhigh td(DSL-HRDYH)12 5 Delay time, DS high to UHPI_HRDYhigh td(DSH-HRDYH)12 6 Delay time, DS low to UHPI_HRDYlow td(DSL-HRDYL)Case 1.

45、 HPID read with no auto increment 10*2H+20 11/ Case 2. HPID read with auto increment and read FIFO initially empty 10*2H+20 11/ 7 Delay time, HD valid to UHPI_HRDYlow td(HDV-HRDYL)0 34 Delay time, DS high to UHPI_HRDYlow td(DSH-HRDYL) Case 1. HPIA write 5*2H+20 11/ Case 2. HPID read with auto increm

46、ent and read FIFO initially empty 5*2H+20 11/ 35 Delay time, DS low to UHPI_HRDYlow for HPIA write and FIFO not empty td(DSL-HRDYL)40*2H+20 11/ 36 Delay time, UHPI_HASlow to UHPI_HRDYhigh td(HASL-HRDYH)12 See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permit

47、ted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11617 REV PAGE 9 TABLE I. Electrical performance characteristics Continued. 1/ No Test Symbol Conditions 2/ Limits Unit Min Max McASP ELECTRICAL DATA/TIMING (See figure 22 24) McASP timing requirements 12/ 8/ 1 Cyc