DLA DSCC-VID-V62 12602-2013 MICROCIRCUIT DIGITAL COMPOLETE DDR DDR2 AND DDR3 MEMORY POWER SOLUTION SYNCHRONOUS BUCK CONTROLLER 3 A LDO BUFFERED REFERENCE MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Origina

2、l date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, COMPOLETE DDR, DDR2 AND DDR3 MEMORY POWER SOLUTION SYNCHRONOUS BUCK CONTROLLER, 3 A LDO, BUFFERED REFERENCE, MONOLITHIC SILICON 13-01-28 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12602 REV PAGE

3、 1 OF 12 AMSC N/A 5962-V078-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12602 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high

4、 performance complete DDR, DDR2 and DDR3 memory power solution synchronous buck controller, 3-A LDO, buffered reference microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The

5、vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/12602 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TPS5111

6、6-EP Complete DDR, DDR2 and DDR3 memory power solution synchronous buck controller, 3-A LDO, buffered reference 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 20 JEDEC MO-153 Plastic small outline 1.2.3 Lead finishes. The

7、lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Input voltage range, (VIN): VBST . -0.3 V to 36.0

8、V VBST wrt LL -0.3 V to 6.0 V CS, MODE, S3, S5, VTTSNS, VDDQSNS, V5IN, VLDOIN, VDDQSET . -3.0 V to 6.0 V PGND, VTTGND . -0.3 V to 0.3 V Output voltage range, (VOUT): DVRH -1.0 V to 36.0 V LL -1.0 V to 30.0 V LL, pulse width 4.5 V, PGOOD = HI 4 10 20 A VCS 4.5 V, PGOOD = LO 2 5 10 TRIP current temper

9、ature coefficient TCITRIPRDS(on) sense scheme, On the basic of TA= 25C 3/ 4500 ppm/C Over current protection COMP offset VOCL(off)(VV5IN-CS VPGND-LL), VV5IN-CS = 60 mV, VCS 4.5 V -7 0 7 mV Current limit threshold setting range VR(trip)VV5IN-CS30 150 Power good comparator VDDQ power good threshold VT

10、VDDQPGPG in from lower 92 95 98 % PG in from higher 102 105 108 % PG hysteresis 5 % PGOOD sink current IPG(max) VVTT= 0 V, VPGOOD= 0.5 V 2.3 7.5 mA PGOOD delay time TPG(del)Delay for PG in 78 130 205 s See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted

11、 without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12602 REV PAGE 8 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ Limits Unit Min Max Undervoltage Lockout/Logic Threshold V5IN UVLO threshold voltage VUV

12、V5INWake up 3.6 4 4.4 V Hysteresis 0.19 0.3 0.41 MODE threshold VTHMODENo discharge 4.7 Non tracking discharge 0.08 VDDQSET threshold voltage VTHVDDQSET2.5 V output 0.075 0.150 0.255 1.8 V output 3.45 4 4.55 High level input voltage VIHS3, S5 2.2 Low level input voltage VILS3, S5 0.3 Hysteresis volt

13、age VIHYSTS3, S5 0.2 Logic input leakage current VINLEAKS3, S5, MODE -1 1 A Input leakage/bias current VINVDDQSETVDDQSET -1 1 Undervoltage and overvoltage protection VDDQ OVP trip threshold voltage VOVPOVP detect 109 115 120 % Hysteresis 5 % VDDQ OVP propagation delay tOVPDEL1.5 s Output UVP trip th

14、reshold VUVPUVP detect 70 % Hysteresis 10 % Output UVP propagation delay TUVPDEL32 cycle Output UVP enable delay TUVPEN1007 Thermal Shutdown Thermal SDN threshold 3/ TSDNShutdown temperature 160 C Hysteresis 10 1/ Testing and other quality control techniques are used to the extent deemed necessary t

15、o assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design

16、. 2/ TJ= -55C to 125C, TJ= TA, VV5IN= 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted). 3/ Specified by design. Not production test. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDEN

17、T NO. 16236 DWG NO. V62/12602 REV PAGE 9 Case X e bE E1D1020AA10.10 MSEE DETAIL ASEATINGPLANE0.10cL0-80.25(.010)GAGEPLANEDETAIL A11THERMALPAD1Dimensions Symbol Millimeters Symbol Millimeters Min Max Min Max A 1.20 E 4.30 4.50 A1 0.05 0.15 E1 6.20 6.60 b 0.19 0.30 e 0.65 BSC c 0.25 TYP L 0.50 0.70 D

18、6.40 6.60 NOTES: 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusions. Mold flash and protrusion shall not exceed 0.15 per side. 4. This package is designed to be soldered to a thermal pad on the

19、 board. Refer to manufacturer for information regarding recommended board layout. 5. See the additional figure in the manufacturer Product data sheet for details regarding the exposed thermal pad features and dimensions. 6. Falls within JEDEC MO-153. FIGURE 1. Case outline. Provided by IHSNot for Re

20、saleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12602 REV PAGE 10 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 VLDOIN 20 VBST 2 VTT 19 DRVH 3 VTTGND 18 LL 4 VTTSN

21、S 17 DRVL 5 GND 16 PGND 6 MODE 15 CS 7 VTTREF 14 V5IN 8 COMP 13 PGOOD 9 VDDQSNS 12 S5 10 VDDQSET 11 S3 FIGURE 2. Terminal connections. Case outline X Terminal I/O Description Name Number COMP 8 I/O Output of the transconductance amplifier for phase compensation. Connect to V5IN to disable gm amplifi

22、er and use D-CAP mode. CS 15 I/O Current sense comparator input (-) for resistor current sense scheme. Or overcurrent trip voltage setting input for RDS(on) current sense scheme if connected to V5IN through the voltage setting resistor DRVH 19 O Switching (top) MOSFET gate drive output. DRVL 17 O Re

23、ctifying (bottom) MOSFET gate drive output. GND 5 Signal ground. Connect to minus terminal of the VTT LDO output capacitor. LL 18 I/O Switching (top) MOSFET gate driver return. Current sense comparator input (-) for RDS(on) current sense MODE 6 I Discharger mode setting pin. See VDDQ and VTT Dischar

24、ger control in manufacturer data. PGND 16 Ground for rectifying (bottom) MOSFET gate driver (PWP, RGE). Also current sense comparator input (+) and ground for powergood circuit (PWP). PGOOD 13 O Powergood signal open drain output. In HIGH state when VDDQ output voltages is within the target range. S

25、3 11 I S3 signal input S5 12 I S5 signal input V5IN 14 I 5 V power supply input for internal circuits (PWP) and MOSFET gate driver (PWP, RGE) VBST 20 I/O Switching (top) MOSFET driver bootstrap voltage input. VDDQSET 10 I VDDQ output voltage setting pin. See VDDQ output voltage selection in manufact

26、urer data. VDDQSNS 9 I/O VDDQ reference input for VTT and VTTREF. Power supply for the VTTREF. Discharger current sinking terminal for VDDQ Non Tracking discharger. Output voltage feedback input for VDDQ output if VDDQSET pin is connected to V5IN or GND. VLDOIN 1 I Power supply for the VTT LDO VTT 2

27、 O Power output for the VTT LDO VTTGND 3 Power ground output for the VTT LDO VTTREF 7 O VTTREF buffered reference output. VTTSNS 4 I Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO output capacitor. FIGURE 3. Terminal function. Provided by IHSNot for ResaleNo reproductio

28、n or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12602 REV PAGE 11 -+-+-+-+-+4.0/3.7 VREF0.7 VV5inOKREFOKREFHalfVDDQ+5/10%-+-+0.75V+5/10%HalfVDDQ-5/10%-+-+0.75V-30%VttOKDELAYPGNDPGOODVddqOKVddqUVVddqOV0.75V-5/10%0.75V

29、+15%1.25 VGND-+VTTGNDVTTPGNDVDDQ_ONVTTLDO_ON0.15 VMODE-+-+VttOK-+-+-LOOP PATHCONTROLREF.75 VDDR2+-+-+-+1 SHOTON/OFF TIMEMINIMUM ON/OFFLIGHT LOAD, OVP/UVPTON 100 ns,TOFF 300 nsXCONCONTROL LOGICDISCHARGE MODESELECT-+ MODE4 VLLVDDQSNSV5INV5INV5IN10/5uA-+LL+-+-DDRDDR2ADJUSTADJUST60/30 mVVddqOKVddqOK4 VR

30、EF0.5 V4 VVDDQSNSPGNDDRVLLLDRVHVBSTS3S5VTTREFVLDOINVTTVTTGNDVTTSNSVDDQSNSVDDQSETCOMPCSTRACKING DISCHARGEHalfVDDQFIGURE 3. Functional block diagram (case X). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A C

31、ODE IDENT NO. 16236 DWG NO. V62/12602 REV PAGE 12 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sens

32、itive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensi

33、tive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to

34、 make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land a

35、nd Maritime maintains an online database of all current sources of supply at http:/www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Top side marking Transport media Vendor part number V62/12602-01XE 01295 51116M Tube TPS51

36、116MPWPEP Tape and real TPS51116MPWPREP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-