DLA DSCC-VID-V62 12607 REV A-2012 MICROCIRCUIT DIGITAL 9 CHANNEL RS-422 RS-485 TRANSCEIVER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Correct vendor part in section 6.3. - phn 12-06-04 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND

2、 MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, 9 CHANNEL RS-422/ RS-485 TRANSCEIVER, MONOLITHIC SILICON 12-05-01 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12607 R

3、EV A PAGE 1 OF 14 AMSC N/A 5962-V059-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12607 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements

4、of a high performance 9 channel RS-422/ RS-485 transceiver microcircuit, with an operating temperature range of -40C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control numb

5、er for identifying the item on the engineering documentation: V62/12607 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN65HVD09-EP 9 channel RS-422/ RS-485 transceiver 1.2.2 Case outline(

6、s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 56 JEDEC MO-153 Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Ho

7、t solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12607 REV PAGE 3 1.3 Absolute maximum r

8、atings. 1/ Supply voltage range, (VCC) . -0.3 V to 6.0 V 2/ Bus voltage range -10 V to 15 V Data I/O and control (A side) voltage range . -0.3 V to VCC+ 0.5 V Receiver output current (IO) . 40 mA Electrostatic discharge: B side and GND, ESD HBM 12 kV B side and GND, ESD MM 400 V All terminals, ESD H

9、BM 4 kV All terminals, ESD MM 400 V Continuous total power dissipation . Internally limited 3/ Dissipation ratings Package TA 25C Operating factor 4/ above TA= 25C TA= 70C Power rating TA= 70C Power rating Case X 2500 mW 20 mW/C 1600 mW 1300 mW Thermal characteristics Typical Unit Junction to ambien

10、t thermal resistance (JA) 50 C/W Junction to case (top) thermal resistance (JA) 27 Thermal shutdown temperature (TSD) 165 C 1.4 Recommended operating conditions. Supply voltage, (VCC) . 4.75 V to 5.25 V Minimum high level input voltage, (VIH) (except nB+, nB-) 5/ 2.0 V Maximum low level input voltag

11、e, (VIL) (except nB+, nB-) 5/ . 0.8 V Voltage at any bus terminal, (VO, VI, VIC) (separately or common mode) (nB+ or nB-) - 7.0 V to 12.0 V Output current: Driver -60 mA to 60 mA Receiver -8 mA to 8 mA Operating free air temperature, (TA) . -40C to 85C 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHN

12、OLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 1/ Stresses beyond those liste

13、d under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated condi

14、tions for extended periods may affect device reliability. 2/ All voltage values are with respect to the GND terminals. 3/ The maximum operating junction temperature is internally limited. Use the Dissipation Rating Table to operate below this temperature. 4/ This is inverse of the junction to ambien

15、t temperature when board mounted and with no air flow. 5/ n = 1 9. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12607 REV PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall

16、be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and wi

17、th items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physic

18、al dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal function shall be as shown in figure 3. 3.5.4 L

19、ogic diagram. The logic diagram shall be as shown in figure 4. 3.5.5 Driver test circuit, RS-422 and RS-485 loading. The driver test circuit, RS-422 and RS-485 loading shall be as shown in figure 5. 3.5.6 Driver test circuit, pull-up and pull down loading. The driver test circuit, pull-up and pull-d

20、own loading shall be as shown in figure 6. 3.5.7 Driver delay and transition time test waveforms. The Driver delay and transition time test waveforms shall be as shown in figure 7. 3.5.8 Receiver propagation delay and transition time test circuit. The receiver propagation delay and transition time t

21、est circuit shall be as shown in figure 8. 3.5.9 Receiver delay and transition time waveforms. The receiver delay and transition time waveforms shall be as shown in figure 9. 3.5.10 Driver enable and disable time test circuit. The driver enable and disable time test circuit shall be as shown in figu

22、re 10. 3.5.11 Driver enable time waveforms. The driver enable time waveforms shall be as shown in figure 11. 3.5.12 Receiver enable and disable time test circuit. The receiver enable and disable time test circuit shall be as shown in figure 12. 3.5.13 Receiver enable and disable time waveforms. The

23、receiver enable and disable time waveforms shall be as shown in figure 13. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12607 REV PAGE 5 TABLE I. Electrical performance c

24、haracteristics. 1/ Test Symbol Conditions 2/ Limits Unit Min Max Driver differential output voltage magnitude |VDD| RS-422 load RL = 100 See figure 5 0.56 V RS-485 load RL = 54 1.4 TYP Pull up Pull-down load See figure 6 1 High level output voltage VOHA side, IOH= -8 mA, VID= 200 mV See figure 8 4 B

25、 side, See figure 6 3 TYP Low level output voltage VOLA side, IOH= 8 mA, VID= -200 mV See figure 8 0.8 B side, See figure 6 1 TYP Receiver positive going differential input threshold voltages VIT+IOH= -8 mA See figure 8 0.2 Receiver negative going differential input threshold voltages VIT-IOH= 8 mA

26、See figure 8 -0.2 Receiver input hysteresis (VIT+ - VIT-)VhysVCC= 5 V, TA = 25C 24 mV Bus input current IIVIH= 12 V, VCC= 5 V Other input at 0 V 1 mA VIH= 12 V, VCC= 0 V 1 VIH= -7 V, VCC= 5 V -0.8 VIH= -7 V, VCC= 0 V -0.8 High level input current IIHnA, BSR, DE/RE, and CRE, VIH= 2 V -100 A CDE0, CDE

27、1, and CDE2 VIH= 2 V 100 Low level input current IILnA, BSR, DE/RE, and CRE, VIH= 0.8 V -100 CDE0, CDE1, and CDE2 VIH= 0.8 V 100 Short circuit output current IOSnB+ on nB- 260 mA High impedance state output current IOZnA See IIHand IILnB+ or nB- See IIISupply current ICCDisabled 10 mA All drivers en

28、abled, no load 60 All receivers enabled, no load 45 Output capacitance COnB+ or nB- to GND 18 TYP pF Power dissipation capacitance 3/ CpdReceiver 40 TYP pF Driver 100 TYP See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-D

29、LA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12607 REV PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ Limits Unit Min Max Driver switching characteristics Propagation delay time, tPHLor tPLH(see figure 6 and 7) tpd2.5 1

30、3.5 ns Pulse skew, | tPHL- tPLH| tsk(p)5 Fall time tfS1 to B, See figure 7 4 TYP Rise time trSee figure 7 8 TYP Enable time, control inputs to active output ten50 Disable time, control inputs to high impedance output tdis225 Propagation delay time, high level to high impedance output tPHZSee figure

31、10 and 11 225 Propagation delay time, low level to high impedance output tPLZ225 Propagation delay time, high impedance to high level output tPZH50 Propagation delay time, high impedance to low level output tPZL50 Receiver switching characteristics Propagation delay time, tPHLor tPLH(see figure 6 an

32、d 7) tpd8 14.5 ns Skew limit, maximum tpd minimum tpd4/ tsk(lim)5 Pulse skew, |tPHL- tPLH| tsk(p)5 Transition time (tror tf) ttSee figure 9 2 TYP Enable time, control inputs to active output ten31 TYP Disable time, control inputs to high impedance output tdis41 TYP Propagation delay time, high level

33、 to high impedance output tPHZSee figure 12 and 13 34 TYP Propagation delay time, low level to high impedance output tPLZ14 TYP Propagation delay time, high impedance to high level output tPZH30 TYP Propagation delay time, high impedance to low level output tPZL30 TYP 1/ Testing and other quality co

34、ntrol techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, produc

35、t performance is assured by characterization and/or design. 2/ Over recommended operating free air temperature range (unless otherwise noted). All typical values are with respect to VCC= 5 V, and TA= 25C. 3/ Cpddetermines the no-load dynamic supply current consumption, IS= CPDx VCCx f + ICC. 4/ This

36、 parameter is applicable at one VCC and operating temperature with the recommended operating conditions and to any two devices. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V

37、62/12607 REV PAGE 7 Case X beD1 282956EE10.08 MAA1SEATINGPLANE0.10SEE DETAIL Ac0-8LDETAIL AGAGEPLANE0.25Dimensions Symbol Millimeters Symbol Millimeters Min Max Min Max A 1.20 E 7.90 8.30 A1 0.05 0.15 E1 6.00 6.20 b 0.17 0.27 e 0.50 TYP c 0.15 NOM L 0.50 0.75 D 13.90 14.10 NOTES: 1. All linear dimen

38、sions are in millimeters. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold protrusions not exceed 0.15. 4. Falls within JEDEC MO-153. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-D

39、LA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12607 REV PAGE 8 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol 1 GND 15 GND 29 1B- 43 GND 2 BSR 16 GND 30 1B+ 44 GND 3 CRE17 GN

40、D 31 2B- 45 VCC4 1A 18 VCC32 2B+ 46 6B- 5 1DE/RE19 5A 33 3B- 47 6B+ 6 3A 20 5DE/RE34 3B+ 48 7B- 7 2DE/RE21 6A 35 4B- 49 7B+ 8 VCC22 6DE/RE36 4B+ 50 8B- 9 3DE/RE23 7A 37 5B- 51 8B+ 10 4A 24 7DE/RE38 5B+ 52 9B- 11 4DE/RE25 8A 39 VCC53 9B+ 12 VCC26 8DE/RE40 GND 54 CDE0 13 GND 27 9A 41 GND 55 CDE1 14 GN

41、D 28 9DE/RE42 GND 56 CDE2 FIGURE 2. Terminal connections. Terminal I/O Description Name No. 1A to 9A 4, 6, 8, 10, 19,21, 23, 25, 27 I/O 1A to 9A carry data to and from the communication controller 1b- to 9B- 29, 31, 33, 35, 37, 46, 48, 50, 52 I/O 1B- to 9B- are the inverted data signals of the balan

42、ced pair to/from the bus 1B+ to 9B+ 30, 32, 34, 36, 38, 47, 49, 51, 53 I/O 1B+ to 9B+ are the noninverted data signals of the balanced pair to/from the bus BSR 2 I BSR is the bit significant response. BSR disables receivers 1 through 8 and enables wired OR drivers when BSR and DE/REand CDE1 and CDE2

43、 are high. Channel 9 is placed in a high impedance state with BSR high CDE0 54 I CDE0 is the common driver enable 0. Its input signal enables all drivers when CDE0 and 1DE/RE- 9DE/REare high. CDE1 55 I CDE1 is the common driver enable 1. Its input signal enables drivers 1 to 4 when CDE1 is high and

44、BSR is low. CDE2 56 I CDE2 is the common driver enable 2. When CDE2 is high and BSR is low, drivers 5 to 8 are enabled. CRE3 I CREis the common receiver enabled. When high, CRE diables receiver channel 5 to 9. 1DE/REto 9DE/RE5, 7, 9, 11, 20, 22, 24, 26, 28 I 1DE/RE- 9DE/REare direction controls that

45、 transmit data to the bus when it and CDE0 are high. Data is received from the bus when 1DE/REto 9DE/REand CRE and BSR are low and CDE1 and CDE2 are low GND 1, 13, 14, 15, 16, 17, 40, 41, 42, 43, 44 Power GND is the circuit ground. All GND terminals except terminal 1 are physically tied to the die p

46、ad for improved thermal conductivity. 1/ VCC12, 18, 39, 45 Power Supply voltage. 1. Terminal 1 must be connected to signal ground for proper operation. FIGURE 3. Terminal function. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME

47、 COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12607 REV PAGE 9 CHANNEL 4CHANNEL 3CHANNEL 22A2DE/RE3A3DE/RE4A4DE/RE1DE/RE1ABSRCDE1CDE04B-4B+3B-3B+2B-2B+1B-1B+CHANNEL 8CHANNEL 7CHANNEL 66A6DE/RE7A7DE/RE8A8DE/RE5DE/RECRECDE28B-8B+7B-7B+6B-6B+5B-5B+5A9B-9B+9DE/RE4ABSR BSR CRE CDE0FIGURE 4. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO S