DLA DSCC-VID-V62 12610-2012 MICROCIRCUIT LINEAR OPERATIONAL AMPLIFIER HIGH PRECISION LOW NOISE MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY R

2、AJESH PITHADIA TITLE MICROCIRCUIT, LINEAR, OPERATIONAL AMPLIFIER, HIGH PRECISION, LOW NOISE, MONOLITHIC SILICON 12-09-19 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12610 REV PAGE 1 OF 11 AMSC N/A 5962-V047-12 Provided by IHSNot for ResaleNo reproduction or networking perm

3、itted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12610 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high precision, low noise, operational amplifier microcircuit, with an operating temperature range

4、 of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/12610 - 01 X E Drawing Device type Case o

5、utline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 OPA2227 High precision, low noise operational amplifier 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package s

6、tyle X 8 MS-012-AA Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot

7、 for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12610 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VS) 18 V Signal input terminals: Voltage . -VS 0.7 V to +VS+ 0.7 V Curr

8、ent . 20 mA Output short circuit (to ground) . Continuous 2/ Junction temperature range (TJ) 150C Storage temperature range (TSTG) -65C to +150C Lead temperature (soldering, 10 seconds) . 300C 1.4 Recommended operating conditions. 3/ Supply voltage range (VS) 5 V to 15 V Operating free-air temperatu

9、re range (TA) . -55C to +125C 1.5 Thermal characteristics. Thermal metric Symbol Case X Unit Thermal resistance, junction-to-ambient 4/ JA91.9 C/W Thermal resistance, junction-to-case (top) 5/ JC(TOP)39.9 C/W Thermal resistance, junction-to-board 6/ JB40.6 C/W Characterization parameter, junction-to

10、-top 7/ JT3.9 C/W Characterization parameter, junction-to-board 8/ JB39.6 C/W 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those

11、indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ One channel per package. 3/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk

12、. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 4/ The thermal resistance, junction-to-ambient under natural convection is obtained in a simulation on a JEDEC standard, high-K board, as specified in JESD51-7, in an environment

13、described in JESD51-2a. 5/ The thermal resistance, junction-to-case (top) is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 6/ The thermal resistance, junction-to-board is obt

14、ained by simulating in an environment with a ring cold plate fixture to control the printed circuit board (PCB) temperature, as described in JESD51-8. 7/ Characterization parameter, junction-to-top (JT) estimates the junction temperature of a device in a real system and is extracted from the simulat

15、ion data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 8/ Characterization parameter, junction-to-board (JB) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JES

16、D51-2a (sections 6 and 7). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12610 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 - R

17、egistered and Standard Outlines for Semiconductor Devices EIA/JESD51-2a - Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) EIA/JEDEC 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages EIA/JESD51-8 - Integrated Circuits

18、 Thermal Test Method Environment Conditions Junction-to-Board (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) ANSI SEMI STANDARD G30-88 - Test Method for Junction-to-Case Thermal Res

19、istance Measurements for Ceramic Packages (Applications for copies should be addressed to the American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org) 3. REQUIREMENTS 3.1 Marking.

20、Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part n

21、umber and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction

22、, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted with

23、out license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12610 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Max Offset voltage Input offset voltage VOS+25C 01 100 V -55C

24、 to +125C 250 Input offset voltage versus temperature VOS/ T +25C 01 0.1 typical V / C Input offset voltage versus power supply VS= 2.5 V to 18 V -55C to +125C 01 2.1 V/V Input offset voltage versus time +25C 01 0.2 typical V / mo Channel separation (dual) CS f = 1 kHz, RL= 5 k +25C 01 110 typical d

25、B Input bias current. Input bias current IIB+25C 01 10 nA Input offset current IOS+25C 01 10 nA Noise. Input voltage noise Vn f = 0.1 Hz to 10 Hz +25C 01 90 typical nVp-p 15 typical nVrms Input voltage noise density en f = 10 Hz +25C 01 3.5 typical nV / f = 100 Hz 3 typical Hz f = 1 kHz 3 typical Cu

26、rrent noise density in f = 1 kHz +25C 01 0.4 typical pA / Hz Input voltage range section. Common mode voltage range VCM-55C to +125C 01 -VS+ 2 +VS- 2 V Common mode rejection ratio CMRR VCM= -VS+ 2 V to +VS 2 V +25C 01 120 dB -55C to +125C 108 See footnotes at end of table. Provided by IHSNot for Res

27、aleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12610 REV PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Max

28、Input impedance section. Differential 3/ Open loop voltage gain +25C 01 107|12 typical |pF Common mode 3/ VCM= -VS+ 2 V to +VS 2 V +25C 01 109| 3 typical |pF Open loop gain section. Open loop voltage gain AOLVO= -VS+ 2 V to +VS 2 V +25C 01 132 dB RL= 10 k -55C to +125C 112 VO= -VS+ 3.5 V to +VS 3.5

29、V +25C 132 RL= 600 -55C to +125C 112 Frequency response section. Gain bandwidth product GBW +25C 01 8 typical MHz Slew rate SR +25C 01 2.3 typical V/s Settling time tS0.1%, G = 1, 10 V step, CL= 100 pF +25C 01 5 typical s 0.01%, G = 1, 10 V step, CL= 100 pF 5.6 typical Overload recovery time VINx G

30、= VS+25C 01 1.3 typical s Total harmonic distortion + noise (THD + N) f = 1 kHz, G = 1, VO= 3.5 Vrms +25C 01 0.00005 typical % Output section. Voltage output VORL= 10 k -55C to +125C 01 -VS+ 2 +VS- 2 V RL= 600 -VS+ 3.5 +VS- 3.5 Short circuit current ISC+25C 01 45 typical mA See footnotes at end of t

31、able. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12610 REV PAGE 7 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TA

32、Device type Limits Unit Min Max Power supply section. Specified voltage range VS +25C 01 5 15 V Operating voltage range +25C 01 2.5 18 V Quiescent current (per amplifier) IQIO= 0 A +25C 01 3.95 mA -55C to +125C 4.30 1/ Testing and other quality control techniques are used to the extent deemed necess

33、ary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or d

34、esign. 2/ Unless otherwise specified, VS= 5 V to 15 V and RL= 10 k. 3/ The | symbolizes that the input impedance is being represented as the resistance value is in parallel with the capacitance. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAN

35、D AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12610 REV PAGE 8 Case X FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12610 R

36、EV PAGE 9 Case X Symbol Dimensions Inches Millimeters Min Max Min Max A - 0.069 - 1.75 A1 0.004 0.010 0.10 0.25 b 0.012 0.020 0.31 0.51 c 0.005 0.010 0.13 0.25 D 0.189 0.197 4.80 5.00 E 0.150 0.157 3.80 4.00 E1 0.228 0.244 5.80 6.20 e 0.050 BSC 1.27 BSC L 0.016 0.050 0.40 1.27 n 8 8 NOTES: 1. Contro

37、lling dimensions are inch, millimeter dimensions are given for reference only. 2. For dimension D, body length does not include mold flash, protrusion, or gate burrs. Mold flash, protrusion, or gate burrs shall not exceed 0.006 inch (0.15 mm) per end. 3. For dimension E, body width does not include

38、interlead flash. Interlead flash shall not exceed 0.017 inch (0.43 mm) per side. 4. Falls with JEDEC MS-012-AA. FIGURE 1. Case outline - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT

39、 NO. 16236 DWG NO. V62/12610 REV PAGE 10 Device type 01 Case outline X Terminal number Terminal symbol 1 OUTPUT A 2 -INPUT A 3 +INPUT A 4 -VS5 +INPUT B 6 -INPUT B 7 OUTPUT B 8 +VSFIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from

40、 IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12610 REV PAGE 11 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedure

41、s should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard

42、commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers da

43、ta book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued avail

44、ability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Top side marking Transport media Vendor part number 2/ 3/ V62/12610-01XE 01295 2227EP Tape and reel OPA2227MDREP Tube OPA2227MDEP 1/ The vendor item drawing establishes an a

45、dministrative control number for identifying the item on the engineering documentation. 2/ For the most current package and ordering information, see the package option addendum at the end of the manufacturers data sheet. 3/ Package drawings, standard packaging quantities, thermal data, symbolizatio

46、n, and printed circuit board (PCB) design guidelines are available from the manufacturer. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-