DLA DSCC-VID-V62 12620-2012 MICROCIRCUIT DIGITAL MIXED SIGNAL MICROCONTROLLER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE 18 19 20 21 REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landa

2、ndmaritime.dla.mil/ Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, MIXED SIGNAL MICROCONTROLLER, MONOLITHIC SILICON 12-12-14 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12620 REV PAGE 1 OF 21 AMSC N/A 5962-V075-12 Provided by IHSNot fo

3、r ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12620 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance mixed signal microcontroller microcircu

4、it, with an operating temperature range of -40C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/12

5、620 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 MSP430G2230-EP Mixed signal microcontroller 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pi

6、ns JEDEC PUB 95 Package style X 8 JEDEC MS-012 Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladi

7、um Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12620 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Voltage applied at VCCto VSS. -0.3 V to 4.1 V Voltage applied to

8、 any pin -0.3 V to VCC+0.3 V 2/ Diode current at any device terminal 2 mA Storage temperature: 3/ Unprogrammed device -55C to 150C Programmed device -40C to 150C 1.4 Recommended operating conditions. Supply voltage, (VCC): During program execution . 1.8 V to 3.6 V During flash program/erase . 2.2 V

9、to 3.6 V Supply voltage, (VSS) 0 V Operating free air temperature, (TA) . -40C to 125C Processor frequency (Maximum MCLK frequency) 4/ 5/ VCC= 1.8 V, Duty cycle = 50% 10% dc to 6 MHz VCC= 2.7 V, Duty cycle = 50% 10% dc to 12 MHz VCC= 3.3 V, Duty cycle = 50% 10% dc to 16 MHz 2. APPLICABLE DOCUMENTS J

10、EDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices J-STD-020 Joint IPC/JEDEC standard for moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices. (Copies of these documents are available online at htt

11、p:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the devic

12、e at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2/ All voltage values referenced to VSS. The JTAG fuse blow voltage, VFBis allowed to e

13、xceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse 3/ Higher temperature may be applied during board soldering according to the current JEDEC J STD 020 specification with peak reflow temperatures not higher than classified on the device label on the

14、shipping boxes or reels. 4/ The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. 5/ Modules might have different maximum input clock specification. See the specification from the manufacturer data sheet.

15、 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12620 REV PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part numb

16、er as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteris

17、tics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case ou

18、tline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal function shall be as shown in figure 3. 3.5.4 Functional block diagram. The functional block diagram shall be as

19、shown in figure 4. 3.5.5 Safe operating area. The safe operating area shall be as shown in figure 5. 3.5.6 POR/Brownout Reset (BOR) vs Supply voltage. The POR/Brownout Reset (BOR) vs Supply voltage shall be as shown in figure 6. 3.5.7 VCC(drop) level with a Square voltage drop to gernerate a POR/Bro

20、wnout signal. The VCC(drop) level with a Square voltage drop to gernerate a POR/Brownout signal shall be as shown in figure 7. 3.5.8 VCC(drop) level with a Triangle voltage drop to gernerate a POR/Brownout signal. The VCC(drop) level with a Triangle voltage drop to gernerate a POR/Brownout signal sh

21、all be as shown in figure 8. 3.5.9 DCO wake-up time from LPM3/4 vs DCO frequency. The DCO wake-up time from LPM3/4 vs DCO frequency waveforms shall be as shown in figure 9. 3.5.10 USI low level output voltage vs output current. The USI low level output voltage vs output current shall be as shown in

22、figure 10. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12620 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ TAVCCLimits Unit Mi

23、n Max Active mode supply current into VCCexcluding external current Active mode (AM) current (1 MHz) IAM, 1MHzfDCO= fMCLK= 1 MHz, fACLK= 0 Hz, Program executes in flash, BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz, CPUOFF = 0, SCG0 = 0 SCG1 = 0, OSCOOFF = 0 2.2 V 220 TYP A 3 V 390 Low power mode Sup

24、ply current (into VCC) Excluding external current Low power mode 0 (LPM0) current 3/ ILPM0, 1MHzfMCLK= 0 MHz, fSMCLK= fCDO= 1 MHz, fACLK= 32,768 Hz, BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 25C 2.2 V 65 TYP A Low power mode 2 (LPM2) current 4/ ILPM2fMCL

25、K= fSMCLK= 0 MHz, fCDO= 1 MHz, fACLK= 32,768 Hz, BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 25C 2.2 V 29 125C 46 Low power mode 3 (LPM3) current 4/ ILPM3, VLOfDCO= fMCLK= fSMCLK= 0 MHz, fACLK= from internal LF oscillator (VLO), CPUOFF = 1, SCG0 = 1, SCG1

26、= 1, OSCOFF = 0 25C 2.2 V 0.7 125C 9.3 Low power mode 4 (LPM4) current 5/ ILPM4fDCO= fMCLK= fSMCLK= 0 MHz, fACLK= 0 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 25C 2.2 V 0.5 85C 1.5 TA= 125C fDCO= fMCLK= fSMCLK= 0 MHz, fACLK= 0 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 2.2 V 7.1 See footnote

27、 at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12620 REV PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/

28、VCCLimits Unit Min Max Schmitt Trigger inputs (Port P1) Positive going input threshold voltage VIT+0.45 VCC0.75 VCCV 3 V 1.35 2.25 Negative going input threshold voltage VIT-0.25 VCC0.55 VCC3 V 0.75 1.65 Input voltage hysteresis (VIT+- VIT-) Vhys3 V 0.3 1.0 Pullup/pulldown resistor RPullFor pullup:

29、VIN= VSSFor pulldown: VIN= VCC20 50 k Input capacitance CIVIN= VSSor VCC5 TYP pF Leakage current (Port P1) High impedance leakage current Ilkg(Px.y)6/ 7/ 3 V 120 nA Outputs (Port P1) High level output voltage VOHI(OHmax)= -6 mA 8/ 3 V VCC 0.3 TYP V Low level output voltage VOLI(OLmax)= 6 mA 8/ 3 V V

30、SS+ 0.3 TYP Output frequency (Port P1) Port output frequency (with load) fPx.yCL= 20 pF, RL= 1 k 9/ 10/ 3 V 12 TYP MHz Clock output frequency fPortCLKCL = 20 pF 10/ 3 V 16 TYP POR/Brownout reset (BOR) 11/ See figure 10 VCC(start)dVCC/dt 3 V/s 0.7 x V(B_IT-)TYP V See figure 10 through figure 12 V(B_I

31、T-)dVCC/dt 3 V/s 1 V See figure 10 Vhys(B_IT-)dVCC/dt 3 V/s 140 TYP mV See figure 10 td(BOR)34/ 2000 s Pulse length needed at RST/NMI pin to accept reset internally t(reset)34/ 3 V 2 s See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license

32、from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12620 REV PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ VCCLimits Unit Min Max DCO frequency Supply voltage VCCRSELx VEREF-, SREF1 = 1, SREF0 = 0 1.4 VCCV VERE

33、F- VEREF+ VCC 0.15 V, SREF1 = 1, SREF0 = 1 22/ 1.4 3 Negative external reference input voltage range 23/ VEREF- VEREF+ VEREF- 0 1.2 V Differential external reference input voltage range, VEREF = VEREF+ - VEREF- VEREF VEREF+ VEREF- 24/ 1.4 VCCV Static input current into VEREF+ IVEREF+0 V VEREF+ VCC 0

34、.15 V 3 V, SREF1 = 1, SREF0 = 0 3 V 1 TYP A 0 V VEREF+ VCC 0.15 V 3 V, SREF1 = 1, SREF0 = 1 22/ 3 V 0 TYP Static input current into VEREF- IVEREF-0 V VEREF- VCC3 V 1 TYP A See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-

35、DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12620 REV PAGE 12 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ VCCLimits Unit Min Max 10 Bit ADC, Timing parameters 36/ ADC10 input clock frequency fADC10CLKFor specified perform

36、ance of ADC10 linearity parameters ADC10SR = 0 3 V 0.45 6.3 MHz ADC10SR = 1 0.45 1.5 ADC10 built in oscillator frequency fADC10OSCADC10DIVx = 0, ADC10SSELx = 0, fADC10CLK= fADC10OSC3 V 3.7 6.3 MHz Conversion time tCONVERTADC10 built in oscillator, ADC10SSELx = 0, fADC10CLK= fADC10OSC3 V 2.06 3.51 s

37、fADC10CLKfrom ACLK, MCLK, or SMCLK: ADC10SSELx 0 13 x ADC10DIV x 1/fADC10CLKTurn on setting time of the ADC tADC10ON25/ 100 ns 10 Bit ADC, Linearity parameters 36/ Integral linearity error EI3 V 1 LSB Differential linearity error ED3 V 1 Offset error EOSource impedance RS 100 3 V 1 Gain error EG3 V

38、2 Total unadjusted error ET3 V 5 10 Bit ADC, Temperature sensor and built in VMID36/ Temperature sensor supply current 26/ ISENSORREFON = 0, INCHx = 0Ah, TA= 25C 3 V 60 TYP A TCSENSORADC10ON = 1 INCHx = 0Ah 27/ 3 V 3.55 TYP mV/C Sample time required if channel 10 is selected 28/ tSensor(sample)ADC10

39、ON = 1 INCHx = 0Ah, Error of conversion result 1 LSB 3 V 30 s Current into divider at channel 11 IVMIDADC10ON = 1 INCHx = 0Bh 3 V 29/ A VCCdivider at channel 11 VMIDADC10ON = 1 INCHx = 0Bh, VMID 0.5 x VCC3 V 1.5 TYP V Sample time required if channel 11 is selected 30/ tVMID(sample)ADC10ON = 1 INCHx

40、= 0Bh, Error of conversion result 1 LSB 3 V 1220 ns RAM RAM retention supply voltage 31/ V(RAMh)CPU halted 1.6 V See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO.

41、16236 DWG NO. V62/12620 REV PAGE 13 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ VCCLimits Unit Min Max Spy-Bi-Wire interface Spy-Bi-Wire input frequency fSBW2.2 V/3 V 0 20 MHz Spy-Bi-Wire low clock pulse length tSBW,Low2.2 V/3 V 0.025 15 s Spy-Bi-Wireena

42、ble time (Test high to acceptance of first clock edge 32/) tSBW,EnTA= -40C to 105C 2.2 V/3 V 1 s Spy-Bi-Wire return to normal operation time tSBW,Ret2.2 V/3 V 15 100 s Internal pulldown resistance on TEST RInternalTA= -40C to 105C 2.2 V/3 V 25 90 k JTAG fuse 33/ 37/ Supply voltage during fuse blow c

43、ondition VCC(FB)2.5 V Voltage level on TEST for fuse blow VFB6 7 V Supply current into TEST during fuse blow IFB100 mA Time to blow fuse tFB1 ms 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range.

44、 Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Over recommended operating free air temperature range (unless

45、 otherwise noted). All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. 3/ Current for brownout and WDT clocked by SMCLK included. 4/ Current for brownout and WDT clocked by ACLK included. 5/ Current for brownout included. 6/ The leakage current is measured with VSSor VCC

46、applied to the corresponding pin(s), unless otherwise noted. 7/ The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled. 8/ The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exc

47、eed 48 mA to hold the maximum voltage drop specified. 9/ A resistive divider with two 0.5 k resistors between VCCand VSSis used as load. The output is connected to the center tap of the divider. 10/ The output voltage reaches at least 10% and 90% VCCat the specified toggle frequency. 11/ The current

48、 consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) + Vhys(B_IT-) is 1.8 V.12/ The DCO clock wake up time is measured from the edge of an external wake up signal (for example, port interrupt) to the first clock edge observable externally on a clock