DLA DSCC-VID-V62 12622 REV A-2012 MICROCIRCUIT DIGITAL 16 32 BIT RISC FLASH MICROCONTROLLER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Correct Low level and high level output voltage in section 1.5. Change setup time, SPISOMI before SPICLK low and high, in Table I. - phn 12-12-10 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE 40 41 42 43 REV PAGE 18 19

2、20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Original date of drawing YY-MM-DD CHECKED BY Phu H.

3、 Nguyen TITLE MICROCIRCUIT, DIGITAL, 16/32 BIT RISC FLASH MICROCONTROLLER, MONOLITHIC SILICON 12-08-14 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12622 REV A PAGE 1 OF 43 AMSC N/A 5962-V031-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without licen

4、se from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12622 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 16/32 bit RISC Flash microcontroller microcircuit, with an operating temperature range of -55C to +1

5、25C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/12622 - 01 X E Drawing Device type Case outline Lead fi

6、nish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TMS570LS20206-EP 16/32 bit RISC Flash microcontroller 02 TMS570LS20216-EP 16/32 bit RISC Flash microcontroller 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline let

7、ter Number of pins JEDEC PUB 95 Package style X 144 MS-026 Plastic Quad Flatpack Y 337 MO-275 Plastic Ball Grid Array 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead pl

8、ate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12622 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage

9、range: VCC , -0.3 V to 2.12 V 2/ VCCIO, VCCAD, VCCP (Flash pump) . -0.3 V to 4.1 V 2/ Input voltage ranges, All input pins (VI): -0.3 V to 4.1 V Input clamp current: IIK(VIVCCIO) 20 mA All pins except AD1IN7:0, AD2IN7:0, ADSIN15:8 IIK(VIVCCAD) AD1IN7:0, AD2IN7:0, ADSIN15:8 . 10 Ma Total 40 mA Operat

10、ing free air temperature ranges, (TA) -55C to 125C Storage temperature range (TSTG) . -65C to 150C ESD stress voltage, (VESD) 4/ : Human Body Level (HBL) 5/ . 1000 V Charged Device Model (CDM) 6/ . 500 V 1.4 Recommended operating conditions. 3/ Parameters Symbol Limits Unit Min Max Digital logic sup

11、ply voltage (Core) VCC1.35 1.65 V Digital logic supply voltage (I/O) VCCIO3 3.6 MibDC supply voltage VCCAD3 3.6 Flash pump supply voltage VCCP3 3.6 Digital logic supply ground VSS0 TYP MibADC supply ground VSSAD-0.1 0.1 Operating free air temperature TA-55 125 C Input hysteresis Low level input volt

12、age All input 1.5 Electrical Characteristics over operating free air temperature range. 4/ 6/ Parameters Symbol Test conditions Limits Unit Min Max Input hysteresis Vhys0.15 V Low level input voltage All input 5/ VIL-0.3 0.8 High level output voltage All input VIH2 VCCIO+ 0.3 1/ Stresses beyond thos

13、e listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated

14、 conditions for extended periods may affect device reliability. 2/ All voltage value are with respect to their associate ground. 3/ All voltages are with respect to VSS except VCCADis with respect to VSSAD. 4/ Source currents (out of the device) are negative while sink current (into the device) are

15、positive. 5/ This does not apply to PORRSTpin. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12622 REV PAGE 4 1.5 Electrical Characteristics over operating free air temper

16、ature range - Continued. 6/ Parameters Symbol Test conditions Limits Unit Min Max Low level output voltage VOLIOL= IOLMAX 0.2 VCCIOV IOL= 50 A 0.2 High level output voltage VOHIOH= IOHMAX 0.8 VCCIOIOH= 50 A VCCIO 0.2 Low level input voltage OSCIN VILoscin-0.3 0.2 VCCHigh level input voltage OSCIN VI

17、Hoscin0.8 VCCVCC+ 0.3 Voltage monitoring threshold VCClow VMON1.0 1.35 VCChigh 1.7 2.38 VCCIOlow 2.0 3.0 Input clamp current IICVIVSSIO+ 0.3 -2 2 mA Input current (I/O pins) IILPulldown IIVI= VSS-1 1 A IIHPulldown 20 A VI= VCCIO5 40 IIHPulldown 100 A VI= VCCIO40 195 IILPullup 20 A VI= VSS-40 -3.6 II

18、LPullup 100 A VI= VSS-195 -40 IIHPullup VI= VCCIO-1 1 All other pins No pullup or pulldown -1 1 Low level output current TDO, TDI, TMS, RTCK, ECLK, FRAYTX1, FRAYTXEN1, FRAYTX2, FRAYTXEN2, DMMENA, ETMTRACECTL, ETMTRACECLKOUT, ETMDATA31:0, RTPSYNC, RTPCLK, RTPDATA15:0, EMIFWE, EMIFOE, EMIFCS3: 0, EMIF

19、DATA15:0, EMIFADD21:0, EMIFBAD1:0, EMIFDQM1: 0,ERRORIOLVOL= VOLMAX 8 mA RST, MIBSP1CLK, MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI3CLK, MIBSPI3SIMO, MIBSPI3SOMI, MIBSPI5CLK, MIBSPI5SIMO3:0, MIBSPI5SOMI15:8, DMMDATA4 4 All other input pins 2 See footnote at end of table. Provided by IHSNot for ResaleNo reprodu

20、ction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12622 REV PAGE 5 1.5 Electrical Characteristics over operating free air temperature range - Continued. 6/ Parameters Symbol Test conditions Limits Unit Min Max High

21、 level output current TDO, TDI, TMS, RTCK, ECLK, FRAYRX1, FRAYTX1, FRAYTXEN1, FRAYRX2, FRAYTXEN2, ETMTRACECTL, ETMTRACECLKOUT, ETMDATA31:0, RTPSYNC, RTPCLK, RTPDATA15:0, DMMENA, EMIFWE, EMIFOE, EMIFCS3: 0, EMIFDATA15:0, EMIFADD21:0, EMIFBAD1:0, EMIFDQM1: 0, ERRORIOHVOH= VOHMIN -8 mA RST, MIBSP1CLK,

22、MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI3CLK, MIBSPI3SIMO, MIBSPI3SOMI, MIBSPI5CLK, MIBSPI5SIMO3:0, MIBSPI5SOMI15:8, DMMDATA4 -4 All other input pins -2 VCCdigital supply current (Operating mode) All packages ICCHCLK = 100MHz, VCLK = 100MHz 350 mA HCLK = 140MHz, VCLK = 70MHz 390 Case Y package HCLK = 160MHz

23、, VCLK = 80MHz 430 VCCdigital supply current (CPU selftest mode: LBIST) 7/ 8/ All packages STCCLK = 46.666MHz Peak 510 STCCLK = 50MHz Peak 540 Case Y package STCCLK = 53.333MHz Peak 580 VCCdigital supply current (Mem selftest mode: PBIST) 7/ 9/ All packages HCLK = 800MHz, VCLK = 40MHz Peak 340 HCLK

24、= 100MHz, VCLK = 100MHz Peak 430 VCCdigital supply current (doze mode) OSCIN = 6 MHz, VCC= 1.65 V 10/ 35 VCCdigital supply current (snooze mode) All frequencies, VCC= 1.65 V 10/ 30 VCCdigital supply current (sleep mode) All frequencies, VCC= 1.65 V 10/ 25 VCCIOdigital supply current (operating mode)

25、 ICCIONo DC load, VCCIO= 3.6 V 11/ 15 mA VCCIOdigital supply current (doze mode) No DC load, VCCIO= 3.6 V 11/ 700 A VCCIOdigital supply current (snooze mode) No DC load, VCCIO= 3.6 V 11/ 100 VCCIOdigital supply current (sleep mode) No DC load, VCCIO= 3.6 V 11/ 100 See footnote at end of table. Provi

26、ded by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12622 REV PAGE 6 1.5 Electrical Characteristics over operating free air temperature range - Continued. 6/ Parameters Symbol Test c

27、onditions Limits Unit Min Max VCCADsupply current (operating mode) ICCADAll frequencies, VCCAD= 3.6 V 30 mA VCCADsupply current (doze mode) All frequencies, VCCAD= 3.6 V 10/ 200 A VCCADsupply current (snooze mode) All frequencies, VCCAD= 3.6 V 10/ 200 VCCADsupply current (sleep mode) All frequencies

28、, VCCAD= 3.6 V 10/ 200 VCCPpump supply current ICCPVCCP= 3.6 V read operation 25 mA VCCP= 3.6 V program 12/ 90 VCCP= 3.6 V erase 90 VCCP= 3.6 V doze mode 10/ 5 A VCCP= 3.6 V snooze mode 10/ 5 VCCP= 3.6 V sleep mode 10/ 5 Input capacitance 13/ CI2 TYP pF Output capacitance CO3 TYP Thermal resistance

29、characteristics : Parameter Case outline X Case outline Y Unit Junction to ambient thermal resistance, JA14/ 32.1 30.7 C/W Junction to case (top) thermal resistance, JCtop15/ 3.3 4.7 Junction to board thermal resistance, JB16/ 13.7 15 Junction to top characterization parameter, JT17/ 0.1 0.1 Junctio

30、n to board characterization parameter, JB18/ 13.3 15 Junction to case (bottom) thermal resistance, JCbot19/ N/A N/A _ 6/ Typical values are at VCC= 1.5 V and maximum are at VCC= 1.65 V. 7/ The peak current is measured on the manufacturer EVM board with two 10 F and thirteen 100 nF capacitors on VCC

31、domain. Running at a lower frequency consumes less current. 8/ LBIST currents specified are for execution of LBIST with a certain STC clock. Lower current consumption can be achieved by configuring a slower STC clock frequency. The current peak duration can last for the duration of 1 LBIST test inte

32、rval. 9/ PBIST current specified are for execution of PBIST on all RAMs (group 1-14) and all algorithms. Lower current consumption can be achieved by configuring a slower HCLK frequency. Different algorithms consume different current. For more information, please refer to the manufacturer data. 10/

33、For Flash banks/pump in sleep mode. 11/ I/O pins configured as inputs or outputs with no load. All pulldown inputs 0.2 V. All pullup inputs VCCIO 0.2 V. 12/ This assumes reading from one bank while programming a different bank. 13/ The maximum input capacitance CIof the FlexRay RX pin(s) is 10 pF. 1

34、4/ The junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC standard, high K board, as specified in JEDEC 51-7, in an environment described in JESD51-2a. 15/ The junction to case (top) thermal resistance is obtained by simulating a cold plate test on

35、 the package top. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 16/ The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in J

36、ESD51-8. 17/ The junction to top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 18/ The junction to board characterization paramet

37、er, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 19/ The junction to case (bottom) thermal resistance is obtained by simulating a cold plate test on the exp

38、osed (power) pad. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO.

39、 V62/12622 REV PAGE 7 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) JESD51-7 High Effective Thermal Condu

40、ctivity Test Board for Leaded Surface Mount Packages J-STD-020 Joint IPC/JEDEC standard for moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices. JESD51-8 Junction-to-board thermal resistance Theta-JB or RJB (Copies of these documents are available online at h

41、ttp:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, C

42、AGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electri

43、cal performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figur

44、e 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Functional block diagram. The functional block diagram shall be as shown in figure 3. 3.5.4 Wait states. The wait states shall be as shown in figure 4. 3.5.5 ECLK timing diagram. The ECLK timing diagram sh

45、all be as shown in figure 5. 3.5.6 PORRST timing diagram. The PORRST timing diagram shall be as shown in figure 6. 3.5.7 JTAG timing. The JTAG timing shall be as shown in figure 7. 3.5.8 CMOS level outputs. The CMOS level outputs shall be as shown in figure 8. Provided by IHSNot for ResaleNo reprodu

46、ction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12622 REV PAGE 8 3.5.9 CMOS level inputs. The CMOS level inputs shall be as shown in figure 9. 3.5.10 SPI Master mode external timing (Clock Phase = 0). The SPI Mas

47、ter mode external timing (Clock Phase = 0) shall be as shown in figure 10. 3.5.11 SPI Master mode chip select timing (Clock Phase = 0). The SPI Master mode chip select timing (Clock Phase = 0) shall be as shown in figure 11. 3.5.12 SPI Master mode external timing (Clock Phase = 1). The SPI Master mode external timing (Clock Phase = 1) shall be as shown in figure 12. 3.5.13 SPI Master mode chip select timing (Clock Phase = 1). The SPI Master mode chip select tim