DLA DSCC-VID-V62 12624-2012 MICROCIRCUIT LINEAR LOW VOLTAGE 1 10 LVPECL WITH SELECTABLE INPUT CLOCK DRIVER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/

2、 Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, LINEAR, LOW VOLTAGE 1:10 LVPECL WITH SELECTABLE INPUT CLOCK DRIVER, MONOLITHIC SILICON 12-12-21 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12624 REV PAGE 1 OF 15 AMSC N/A 5962-V079-12 Provid

3、ed by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12624 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low voltage 1:10 LVPECL

4、with selectable input clock driver microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the

5、item on the engineering documentation: V62/12624 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 CDCLVP111-EP Low voltage 1:10 low voltage positive emitter coupled logic (LVPECL) with selec

6、table input clock driver 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 32 See figure 1 Plastic quad flat pack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the devic

7、e manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG

8、NO. V62/12624 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage (VCC) (relative to VEE) . -0.3 V to 4.6 V Input voltage (VIN) -0.3 V to VCC+ 0.5 V Output voltage (VOUT) . -0.3 V to VCC+ 0.5 V Input current (IIN) . 20 mA Negative supply voltage (VEE) (relative to VCC) -4.6 V to 0.3 V Sink/so

9、urce current (IBB) -1 mA to 1 mA DC output current (IO) -50 mA Storage temperature range (TSTG) -65C to +150C Maximum operating junction temperature (TJ) . +150C 1.4 Recommended operating conditions. 2/ Supply voltage (VCC) (relative to VEE) . 2.375 V to 3.8 V Operating junction temperature range (T

10、J) -55C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not imp

11、lied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product

12、 used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12624 REV PAGE 4 1.5 Package thermal impedance. Thermal metric Symbol Test condition Limit Un

13、it Thermal resistance, junction-to-ambient 3/ JA0 LFM 74 C/W 150 LFM 66 C/W 250 LFM 64 C/W 500 LFM 61 C/W Thermal resistance, junction-to-case (top) JC39 C/W 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices EIA/J

14、EDEC 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be

15、 permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with

16、 items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical

17、 dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Truth table. The truth table shall be as shown in figure 3. _ 3/ According to JED

18、EC 51-7 standard. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12624 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VSUPPLY: VCC= 0

19、 V, VEE= -2.375 V to -3.8 V, unless otherwise specifiedTemperature, TJDevice type Limits Unit Min Max Supply internal current IEEAbsolute value of current -55C to +125C 01 35 85 mA Output and internal supply current ICCAll outputs terminated 50 to -55C, +25C 01 385 mA VCC 2 V +125C 405 Input current

20、 IIN Includes pull up/pull down resistors, -55C to +125C 01 -150 150 A VIH= VCC, VIL= VCC 2V Internally generated bias voltage VBBVEE= -3 V to -3.8 V, IBB= -0.2 mA -55C to +125C 01 -1.45 -1.125 V VEE= -2.375 V to -2.75 V, IBB= -0.2 mA -1.4 -1.1 High level input voltage (CLK_SEL) VIH-55C to +125C 01

21、-1.165 -0.88 V Low level input voltage (CLK_SEL) VIL-55C to +125C 01 -1.81 -1.475 V Input amplitude voltage (CLKn, CLKn ) VIDDifference of input, |VIH VIL| 2/ -55C to +125C 01 0.5 1.3 V Common mode voltage (CLKn, CLKn ) VCMDC offset relative to VEE-55C to +125C 01 VEE+ 1 -0.3 V High level output vol

22、tage VOHIOH= -21 mA -55C 01 -1.26 -0.85 V +25C -1.2 -0.85 +125C -1.15 -0.80 Low level output voltage VOLIOL= -5 mA +25C 01 -1.85 -1.425 V -55C, +125C -1.85 -1.25 Differential output voltage swing VODTerminated with 50 to VCC 2 V, see figure 4 -55C to +125C 01 400 mV See footnotes at end of table. Pr

23、ovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12624 REV PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions VSUPPLY: VCC= 2.375 V to

24、3.8 V, VEE= 0 V, unless otherwise specifiedTemperature, TJDevice type Limits Unit Min Max Supply internal current IEEAbsolute value of current -55C to +125C 01 35 85 mA Output and internal supply current ICCAll outputs terminated 50 to VCC 2 V -55C, +25C 01 385 mA +125C 405 Input current IINIncludes

25、 pull up/pull down resistors, -55C to +125C 01 -150 150 A VIH= VCC, VIL= VCC 2V Internally generated bias voltage VBBVCC= -3 V to -3.8 V, IBB= -0.2 mA -55C to +125C 01 VCC-1.45 VCC-1.125 V VCC= 2.375 V to 2.75 V, IBB= -0.2 mA VCC-1.4 VCC-1.1 High level input voltage (CLK_SEL) VIH-55C to +125C 01 VCC

26、-1.165 VCC-0.88 V Low level input voltage (CLK_SEL) VIL-55C to +125C 01 VCC-1.81 VCC-1.475 V Input amplitude voltage (CLKn, CLKn ) VIDDifference of input, |VIH VIL| 2/ -55C to +125C 01 0.5 1.3 V Common mode voltage (CLKn, CLKn ) VCMDC offset relative to VEE-55C to +125C 01 1 VCC-0.3 V High level out

27、put voltage VOHIOH= -21 mA -55C 01 VCC-1.26 VCC-0.85 V +25C VCC-1.2 VCC-0.85 +125C VCC-1.15 VCC-0.80 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG N

28、O. V62/12624 REV PAGE 7 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions VSUPPLY: VCC= 2.375 V to 3.8 V, VEE= 0 V, unless otherwise specifiedTemperature, TJDevice type Limits Unit Min Max Low level output voltage VOLIOL= -5 mA +25C 01 VCC-1.85 VCC-1.425 V -55C, +1

29、25C VCC-1.85 VCC-1.25 Differential output voltage swing VODTerminated with 50 to VCC 2 V, see figure 4 -55C to +125C 01 400 mV See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A

30、CODE IDENT NO. 16236 DWG NO. V62/12624 REV PAGE 8 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions VSUPPLY: VCC= 0 V, VEE= -2.375 V to -3.8 V, unless otherwise specified or VSUPPLY: VCC= 2.375 V to 3.8 V, VEE= 0 V, unless otherwise specifiedTemperature, TJDevice t

31、ype Limits Unit Min Max Differential propagation delay CLKn, CLKn to all Q0, Q0 Q9, Q9 tpd-55C to +125C 01 200 355 ps Output to output skew tsk(o)See figure 5 -55C to +125C 01 50 ps Additive phase jitter tajIntegration bandwidth of 20 kHz to 20 MHz, fout = 200 MHz at 25C -55C to +125C 01 0.8 ps Maxi

32、mum frequency f(max)Functional up to 3.5 GHz, see figure 4 -55C to +125C 01 3500 MHz Output rise and fall time (20%, 80%) tr/ tfSee note 4 in figure 5 -55C to +125C 01 240 ps 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over th

33、e specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ VIDminimum and maximum is requi

34、red to maintain ac specifications, actual device function tolerates a minimum VIDof 100 mV. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12624 REV PAGE 9 Case X FIGURE 1.

35、 Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12624 REV PAGE 10 Case X continued. Symbol Dimensions Inches Millimeters Min Max Min Max A - 0.062 - 1.60 A1 0

36、.053 0.057 1.35 1.45 A2 - 0.009 - 0.25 A3 0.001 MIN 0.05 MIN b 0.009 0.017 0.25 0.45 c 0.005 NOM 0.13 NOM D/E 0.346 0.362 8.80 9.20 D1/E1 0.267 0.283 6.80 7.20 D2/E2 0.220 TYP 5.60 TYP e 0.031 BSC 0.80 BSC L 0.017 0.029 0.45 0.75 NOTES: 1. Controlling dimensions are inch, millimeter dimensions are g

37、iven for reference only. FIGURE 1. Case outline - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12624 REV PAGE 11 Device type 01 Case outline X Terminal number

38、Terminal symbol Terminal number Terminal symbol 1 VCC17 Q6 2 CLK_SEL 18 Q6 3 CLK0 19 Q5 4 CLK 0 20 Q5 5 VBB21 Q4 6 CLK1 22 Q4 7 CLK 1 23 Q3 8 VEE24 Q3 9 VCC25 VCC10 Q9 26 Q2 11 Q9 27 Q2 12 Q8 28 Q1 13 Q8 29 Q1 14 Q7 30 Q0 15 Q7 31 Q0 16 VCC32 VCCFIGURE 2. Terminal connections. Provided by IHSNot for

39、 ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12624 REV PAGE 12 Terminal symbol Description CLK_SEL Clock select. Used to select between CLK0 and CLK1 input pairs. Low voltage transistor-transi

40、stor logic (LVTTL) / low voltage complementary metal oxide semiconductor (LVCMOS) functionality compatible. CLK0, CLK 0 Differential low voltage emitter coupled logic (LVECL) / LVPECL input pair CLK1, CLK 1 Differential LVECL/LVPECL input pair Q(9:0) LVECL/LVPECL clock outputs, these outputs provide

41、 low-skew copies of CLKn. Q (9:0) LVECL/LVPECL complementary clock inputs, these outputs provide copies of CLKn . VBBReference voltage output for single ended input operation. VCCSupply voltage. VEEDevice ground or negative supply voltage in emitter coupled logic (ECL) mode. FIGURE 2. Terminal conne

42、ctions - continued. CLK_SEL Active clock input 0 CLK0, CLK0 1 CLK1, CLK1 FIGURE 3. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12624 REV PAGE 13 FIGURE 4. D

43、ifferential output voltage swing graph. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12624 REV PAGE 14 NOTES: 1. Output skew tsk(0),is calculated as the greater of: the d

44、ifference between the fastest and the slowest tPLHn(n = 0, 1, 9) or the difference between the fastest and the slowest tPHLn(n = 0, 1,9). 2. Part to part skew tsk(pp), is calculated as the greater of: the difference between the fastest and the slowest tPLHn(n = 0, 1,9) across multiple devices or the

45、 difference between the fastest and the slowest tPHLn(n = 0, 1, 9) across multiple devices. 3. Typical values measured at ambient when clock input is 155.52 MHz for an integration bandwidth of 20 kHz to 5 MHz. 4. Input conditions: VCM= 1 V, VID= 0.5 V, and fIN= 1 GHz FIGURE 5. Waveform for calculati

46、ng both output and part to part skew. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12624 REV PAGE 15 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer

47、is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers stand