DLA DSCC-VID-V62 12647-2012 MICROCIRCUIT DIGITAL-LINEAR 4 CHANNEL 200 kSPS 12 BIT ANALOG-TO-DIGITAL CONVERTER WITH SEQUENCER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.m

2、il/ Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, DIGITAL-LINEAR, 4 CHANNEL, 200 kSPS, 12 BIT ANALOG-TO-DIGITAL CONVERTER WITH SEQUENCER, MONOLITHIC SILICON 12-12-20 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12647 REV PAGE 1 OF 16 AMSC

3、N/A 5962-V017-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12647 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 4

4、 channel, 200kSPS 12 bit analog to digital with sequencer microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control numb

5、er for identifying the item on the engineering documentation: V62/12647 - 01 X B Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 AD7923 4 channel, 200kSPS 12 bit analog to digital with sequencer 1.2

6、.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 MO-153-AB Plastic thin shrink small outline package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufactur

7、er: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/1264

8、7 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Analog power supply voltage (AVDD) to analog ground (AGND) . -0.3 V to +7 V Logic power supply input (VDRIVE) to GND -0.3 V to AVDD+ 0.3 V Analog input voltage to AGND . -0.3 V to AVDD+ 0.3 V Digital input voltage to AGND . -0.3 V to 7 V Digital output v

9、oltage to AGND -0.3 V to AVDD+ 0.3 V Reference input (REFIN) to AGND -0.3 V to AVDD+ 0.3 V Input current to any pin except supplies . 10 m A 2/ Power dissipation (PD) . 450 mW Junction temperature range (TJ) 150C Storage temperature range (TSTG) -65C to +150C Lead temperature, soldering : Vapor phas

10、e (60 seconds) . 215C Infrared (15 seconds) . 220C Lead free temperature, soldering reflow . 260(+0) C Electrostatic discharge (ESD) 1.5 kV Thermal impedance, junction to case(JC) 27.6C/W Thermal impedance, junction to ambient (JA) 150.4C/W 1.4 Recommended operating conditions. 3/ Supply voltage (AV

11、DD) range . +2.7 V to +5.25 V Operating free-air temperature range (TA) . -55C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions bey

12、ond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Transient currents of up to 100 mA do not cause silicon controlled rectifier (SCR) latch up. 3/ Use of this product beyond

13、 the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA

14、 LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12647 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arling

15、ton, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.

16、2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I

17、herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Load circuit for digital output timing specifications. The load circuit for digital output timing specifications shall be as shown in figure 1. 3.5

18、.2 Case outline. The case outline shall be as shown in 1.2.2 and figure 2. 3.5.3 Terminal connections. The terminal connections shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A

19、 CODE IDENT NO. 16236 DWG NO. V62/12647 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/Temperature, TA Device type Limits Unit Min Max Dynamic performance. fIN= 50 kHz sine wave, fSCLK= 20 MHz Signal to SINAD At 5 V -40C to +85C 01 70 dB (noise + distortion)

20、+85C to +125C 69 At 3 V -40C to +125C 69 Signal to noise ratio SNR -55C to +125C 01 70 dB Total harmonic distortion THD At 5 V -55C to +125C 01 -77 dB At 3 V -73 Peak harmonic or spurious noise SFDR At 5 V -55C to +125C 01 -78 dB At 3 V -76 Intermodulation distortion (IMD). fA= 40.1 kHz, fB= 41.5 kH

21、z Second order terms -55C to +125C 01 -90 typical dB Third order terms -55C to +125C 01 -90 typical dB Aperture delay -55C to +125C 01 10 typical ns Aperture jitter -55C to +125C 01 50 typical ps Channel to channel isolation fIN= 400 kHz -55C to +125C 01 -85 typical dB Full power bandwidth FPBW 3 dB

22、 -55C to +125C 01 8.2 typical MHz 0.1 dB 1.6 typical DC accuracy. Resolution -55C to +125C 01 12 Bits Integral nonlinearity -55C to +125C 01 1 LSB Differential nonlinearity Guaranteed no missed codes to 12 bits -55C to +125C 01 -0.9 +1.5 LSB See footnotes at end of table. Provided by IHSNot for Resa

23、leNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12647 REV PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TA Device type Limits Unit Min Max

24、DC accuracy continued. 0 V to REFINinput range Straight binary output coding Offset error -55C to +125C 01 8 LSB Offset error match -55C to +125C 01 0.5 LSB Gain error -55C to +125C 01 1.5 LSB Gain error match -55C to +125C 01 0.5 LSB 0 V to 2 x REFINinput range. -REFINto +REFINbiased about REFINwit

25、h twos complement output coding offset Positive gain error -55C to +125C 01 1.5 LSB Positive gain error match -55C to +125C 01 0.5 LSB Zero code error -55C to +125C 01 8 LSB Zero code error match -55C to +125C 01 0.5 LSB Negative gain error -55C to +125C 01 1 LSB Negative gain error match -55C to +1

26、25C 01 0.5 LSB Analog input. Input voltage range VINRange bit set to 1 -55C to +125C 01 0 REFINV Range bit set to 0, AVDD= 4.75 V to 5.25 V 0 2 x REFINDC leakage current -55C to +125C 01 1 A Input capacitance CIN-55C to +125C 01 20 typical pF Reference input. REFINinput voltage 1% specified performa

27、nce -55C to +125C 01 2.5 V DC leakage current -55C to +125C 01 1 A REFINinput impedance fSAMPLE= 200 kSPS -55C to +125C 01 36 typical k See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHI

28、O SIZE A CODE IDENT NO. 16236 DWG NO. V62/12647 REV PAGE 7 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TA Device type Limits Unit Min Max Logic inputs. Input high voltage VINH-55C to +125C 01 0.7 x VDRIVEV Input low voltage VINL-55C to +125C 01

29、 0.3 x VDRIVEV Input current IINVIN= 0 V or VDRIVE-55C to +125C 01 1 A Input capacitance 3/ CIN+ -55C to +125C 01 10 pF Logic outputs. Output high voltage VOHISOURCE= 200 A, AVDD= 2.7 V to 5.25 V -55C to +125C 01 VDRIVE 0.2 V Output low voltage VOLISINK= 200 A -55C to +125C 01 0.4 V Floating state l

30、eakage current -55C to +125C 01 1 A Floating state 3/ output capacitance -55C to +125C 01 1 pF Output coding Coding bit set to 0 -55C to +125C 01 Twos complement Coding bit set to 1 Straight natural binary Conversion rate. Conversion time 16 SCLK cycles, SCLK at 20 MHz -55C to +125C 01 800 ns Track

31、and hold acquisition time Sine wave input -55C to +125C 01 300 ns Full scale step input 300 Throughput rate -55C to +125C 01 200 kSPS Power requirements. Power supply input VDD-55C to +125C 01 2.7 5.25 V Logic power supply input VDRIVE-55C to +125C 01 2.7 5.25 V See footnotes at end of table. Provid

32、ed by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12647 REV PAGE 8 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TA Device type

33、 Limits Unit Min Max Power requirements - continued. Power supply current (IDD). Digital inputs = 0 V or VDRIVEDuring conversion AVDD= 4.75 V to 5.25 V, fSCLK= 20 MHz -55C to +125C 01 2.7 mA AVDD= 2.7 V to 3.6 V, fSCLK= 20 MHz 2.0 Normal mode (static) AVDD= 2.7 V to 5.25 V, SCLK on or off -55C to +1

34、25C 01 600 typical A Normal mode (operational) AVDD= 4.75 V to 5.25 V, fSCLK = 20 MHz, fsample= 200 kSPS -55C to +125C 01 1.5 mA AVDD= 2.7 V to 3.6 V, fSCLK= 20 MHz, fsample= 200 kSPS 1.2 Using auto shutdown mode AVDD= 4.75 V to 5.25 V, fsample= 200 kSPS -55C to +125C 01 900 typical A AVDD= 2.7 V to

35、 3.6 V, fsample= 200 kSPS 650 typical Auto shutdown (static) SCLK on or off -55C to +125C 01 0.5 A Full shutdown mode SCLK on or off -55C to +125C 01 0.5 A Power dissipation . Normal mode (operational) fsample= 200 kSPS, fSCLK= 20 MHz, AVDD= 5 V -55C to +125C 01 7.5 mW fsample= 200 kSPS, fSCLK= 20 M

36、Hz, AVDD= 3 V 3.6 Auto shutdown (static) AVDD= 5 V -55C to +125C 01 2.5 W AVDD= 3 V 1.5 Full shutdown mode AVDD= 5 V -55C to +125C 01 2.5 W AVDD= 3 V 1.5 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARI

37、TIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12647 REV PAGE 9 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 4/Temperature, TA Device type Limits Unit Min Max Timing specification. 5/ Clock frequency 6/ fSCLKAVDD= 3 V and 5 V -55C to +125C 01 10 k

38、Hz 20 MHz Convert timing tCONVERTAVDD= 3 V and 5 V -55C to +125C 01 16 x tSCLKMinimum quiet time required between CS rising edge and start of next conversion tQUIETAVDD= 3 V and 5 V -55C to +125C 01 50 ns CS to SCLK setup time t2AVDD= 3 V and 5 V -55C to +125C 01 10 ns Delay from CS 7/ until DOUT th

39、ree state disabled t3AVDD= 3 V -55C to +125C 01 35 ns AVDD= 5 V 30 Data access time 7/ after SCLK falling edge t4AVDD= 3 V and 5 V -55C to +125C 01 40 ns SCLK low pulse width t5 AVDD= 3 V and 5 V -55C to +125C 01 0.4 x tSCLKns SCLK high pulse width t6AVDD= 3 V and 5 V -55C to +125C 01 0.4 x tSCLKns

40、SCLK to DOUT valid hold time t7AVDD= 3 V and 5 V -55C to +125C 01 10 ns SCLK falling edge 8/ to DOUT high impedance t8AVDD= 3 V -55C to +125C 01 15 45 ns AVDD= 5 V 15 35 DIN setup time prior to SCLK falling edge t9AVDD= 3 V and 5 V -55C to +125C 01 10 ns DIN hold time after SCLK falling edge t10AVDD

41、= 3 V and 5 V -55C to +125C 01 5 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12647 REV PAGE 10 TABLE I. Electrical performance characte

42、ristics Continued. 1/ Test Symbol Conditions 4/Temperature, TA Device type Limits Unit Min Max Timing specification - continued. 5/ 16th SCLK falling edge to CS high t11AVDD= 3 V and 5 V -55C to +125C 01 20 ns Power up time from full power down/ auto shutdown t12AVDD= 3 V and 5 V -55C to +125C 01 1

43、s 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of sp

44、ecific parametric testing, product performance is assured by characterization and/or design. 2/ Unless otherwise specified, VDD= VDRIVE= 2.7 V to 5.25 V, REFIN= 2.5 V, and fSCLK= 20 MHz. 3/ Sample tested at 25C to ensure compliance. 4/ Unless otherwise specified, VDD= 2.7 V to 5.25 V, VDRIVE AVDD, a

45、nd REFIN= 2.5 V. 5/ Sample tested at 25C to ensure compliance. All input signals are specified with tR= tF= 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V, see figure1. The 3 V operating range spans from 2.7 V to 3.6 V. the 5 V operating range spans from 4.75 V to 5.25 V. 6/ The m

46、ark/space ratio for the SCLK input is 40/60 to 60/40. 7/ Measured with the load circuit of figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 VDRIVE. 8/ t8is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of figure 1.

47、 The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, quoted in the timing characteristics t8, is the true bus relinquish time of the part and is independent of the bus loading. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO.