DLA DSCC-VID-V62 12656-2013 MICROCIRCUIT LINEAR 1 2 GHz CLOCK DISTRIBUTION IC 1 6 GHz INPUTS DIVIDERS FIVE OUTPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE 18 19 20 21 22 23 REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www

2、.landandmaritime.dla.mil/ Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, LINEAR, 1.2 GHz CLOCK DISTRIBUTION IC, 1.6 GHz INPUTS, DIVIDERS, FIVE OUTPUTS, MONOLITHIC SILICON 13-01-17 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12656 REV PAGE 1 OF

3、23 AMSC N/A 5962-V041-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12656 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high perfo

4、rmance 1.2 GHz clock distribution IC, 1.6 GHz inputs, dividers, five outputs microcircuit, with an operating temperature range of -55C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administr

5、ative control number for identifying the item on the engineering documentation: V62/12656 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 AD9512-EP 1.2 GHz clock distribution IC, 1.6 GHz in

6、puts, dividers, five outputs 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 48 JEDEC MO-220-VKKD-2 Lead Frame Chip Scale Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provi

7、ded by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDEN

8、T NO. 16236 DWG NO. V62/12656 REV PAGE 3 1.3 Absolute maximum ratings. 1/ VS with respect to GND -0.3 V to +3.6 V DSYNC/DSYNCB with respect to GND . -0.3 V to VS+ 0.3 V RSET with respect to GND . -0.3 V to VS+ 0.3 V CLK1, CLK1B, CLK2, CLK2B with respect to GND . -0.3 V to VS+ 0.3 V CLK1 with respect

9、 to CLK1B . -1.2 V to +1.2 V CLK2 with respect to CLK2B . -1.2 V to +1.2 V SCLK, SDIO, SDO, CSB with respect to GND -0.3 V to VS+ 0.3 V OUT0, OUT1, OUT2, OUT3, OUT4 with respect to GND . -0.3 V to VS+ 0.3 V FUNCTION with respect to GND . -0.3 V to VS+ 0.3 V SYNC STATUS with respect to GND -0.3 V to

10、VS+ 0.3 V Storage temperature range . -65C to 150C Junction temperature 150C Lead temperature (10 sec) 300C 1.4 Thermal characteristics. Thermal resistance 2/ Case outline JAUnit Case X 28.5 C/W 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Ou

11、tlines for Semiconductor Devices JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.

12、) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 1/ Stresses beyond those listed under “absolute maxim

13、um ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended peri

14、ods may affect device reliability. 2/ Thermal impedance measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT N

15、O. 16236 DWG NO. V62/12656 REV PAGE 4 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics ar

16、e as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The ter

17、minal connections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal function shall be as shown in figure 3. 3.5.4 Functional block diagram. The functional block diagram shall be as shown in figure 4. 3.5.5 LVPECL differential output swing vs frequency. The LVPECL differential outp

18、ut swing vs frequency shall be as shown in figure 5. 3.5.6 LVDS differential output swing vs frequency. The LVDS differential output swing vs frequency shall be as shown in figure 6. 3.5.7 CMOS single ended output swing vs frequency and load. The CMOS single ended output swing vs frequency and load

19、shall be as shown in figure 7. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12656 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test conditio

20、ns 2/ Limits Unit Min Typ Max CLOCK INPUTS Clock inputs (CLK1, CLK2) 3/ Input frequency 0 1.6 GHz Input sensitivity 4/ 150 7/ mV p-p Input level 5/ 2 8/ V p-p Input common mode voltage VCM6/ 1.45 1.6 1.7 V At -40C to +85C 1.5 1.6 1.7 V Input common mode range VCMRWith 200 mV p-p signal applied, dc-c

21、oupled 1.3 1.8 V Input sensitivity, single ended CLK2 ac-coupled; CLK2B ac bypassed to RF ground 150 mV p-p Input resistance Self-biased 4.0 4.8 5.6 k Input capacitance 2 pF CLOCK OUTPUTS LVPECL clock outputs (Termination = 50 to VS 2 V) OUT0, OUT1, OUT2; Differential Output frequency Output high vo

22、ltage Output low voltage Output differential voltage VOHVOLVODOutput level 0x3D (0x3E) (0x3F)3:2 = 10b See FIGURE 5 VS 1.22 VS 2.10 660 VS 0.98 VS 1.80 810 1200 VS 0.93 VS 1.67 965 MHz V V mV LVDS clock outputs (Termination = 100 differential; default) OUT3, OUT4; Differential Output frequency Diffe

23、rential output voltage Delta VODOutput offset voltage Delta VOSShort Circuit current VOD VOSISA, ISBOutput level 0x40 (0x41)2:1 = 01b 3.5 mA termination current See FIGURE 6 At full temperature range At -40C to +85C Output shorted to GND 250 1.05 1.125 360 1.23 1.23 14 800 450 25 1.375 1.375 25 24 M

24、Hz mV mV V V mV mA CMOS clock outputs OUT3, OUT4 Output frequency Output voltage high Output voltage low VOHVOLSingle ended measurements; B outputs: inverted, termination open With 5 pF load each outputs, see FIGURE 7 1 mA load 1 mA load VS 0.1 250 0.1 MHz V V See footnote at end of table. Provided

25、by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12656 REV PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 2/ Limits Unit Min Typ Ma

26、x TIMING CHARACTERISTICS LVPECL (Termination = 50 to VS 2V, Output level 0x3D (0x3E)(0x3F)3:2 =10b) Output rise time tRP20% to 80%, measured differentially 130 180 ps Output fall time tFP80% to 20%, measured differentially 130 180 Propagation delay, tPELC, CLK-TO-LVPECL OUT 9/ Divide = Bypass At ful

27、l temperature range 320 490 635 ps At -40C to +85C 335 490 635 Divide = 2 to 32 At full temperature range 360 545 695 At -40C to +85C 375 545 695 Variation with temperature 0.5 ps/C Output skew, LVPECL outputs OUT1 to OUT0 on same part 10/ tSKP70 100 140 ps OUT1 to OUT2 on same part 10/ tSKP15 45 80

28、 OUT0 to OUT2 on same part 10/ tSKP45 65 90 All LVPECL OUT across multiple parts 11/ tSKP_AB275 Same LVPECL OUT across multiple parts 11/ tSKP_AB130 LVDS (Termination = 100 differential, Output level 0x40 (0x41)2:1 = 01b, 3.5 mA termination current) Output rise time tRL20% to 80%, measured different

29、ially 200 350 ps Output fall time tFL80% to 20%, measured differentially 210 350 Propagation delay, tLVDS, CLK-to-LVDS OUT 9/ OUT3 to OUT4 Divide = Bypass At full temperature range 0.97 1.33 1.59 ns At -40C to +85C 0.99 1.33 1.59 Divide = 2 to 32 At full temperature range 1.02 1.38 1.64 At -40C to +

30、85C 1.04 1.38 1.64 Variation with temperature 0.9 ps/C Output skew, LVDS outputs OUT3 to OUT4 on same part, 10/ tSKV-85 +270 ps All LVDS OUTs across multiple parts 11/ tSKV_AB450 Same LVDS OUT across multiple parts 11/ tSKV_AB325 See footnote at end of table. Provided by IHSNot for ResaleNo reproduc

31、tion or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12656 REV PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 2/ Limits Unit Min Typ Max TIMING CHARACTERISTICS-Contin

32、ued. CMOS (B outputs are inverted; termination = open) Output rise time tRC20% to 80%, CLOAD= 3 pF 681 865 ps Output fall time tFC80% to 20%, CLOAD= 3 pF 646 992 Propagation delay, tCMOS, CLK to CMOS OUT 9/ Divide = Bypass At full temperature range 1.0 1.39 1.71 ns At -40C to +85C 1.02 1.39 1.71 Div

33、ide = 2 to 32 At full temperature range 1.05 1.44 1.76 At -40C to +85C 1.07 1.44 1.76 Variation with temperature 1 ps/C Output skew, CMOS outputs OUT3 to OUT4 on same part, 10/ tSKC-140 +145 +300 ps All CMOS OUT across multiple parts 11/ tSKC_AB650 Same CMOS OUT across multiple parts 11/ tSKC_AB500

34、LVPECL to LVDS OUT (Everything the same; different logic type LVPECL to LVDS on same part) Output skew tSKP_V0.73 0.92 1.14 ns LVPECL to CMOS OUT (Everything the same; different logic type LVPECL to CMOS on same part) Output skew tSKP_C0.87 1.14 1.43 ns LVDS to CMOS OUT (Everything the same; differe

35、nt logic type LVDS to CMOS on same part) Output skew tSKV_C158 353 506 ps See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12656 REV PAGE 8 TABL

36、E I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 2/ Limits Unit Min Typ Max CLOCK OUTPUT PHASE NOISE CLK1 to LVPECL and additive phase noise CLK1 = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = 1 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 KHz Offset 100 kHz Offse

37、t 1 MHz Offset Input slew rate 1 V/ns -125 -132 -140 -148 -153 -154 dBc/Hz CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 KHz Offset 100 kHz Offset 1 MHz Offset -128 -140 -148 -155 -161 -161 dBc/Hz CLK1 = 622.08 MHz, OUT = 38.88 MHz Divide Ratio = 16

38、10 Hz Offset 100 Hz Offset 1 kHz Offset 10 KHz Offset 100 kHz Offset 1 MHz Offset -135 -145 -158 -165 -165 -166 dBc/Hz CLK1 = 491.52 MHz, OUT = 61.44 MHz Divide Ratio = 8 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 KHz Offset 100 kHz Offset 1 MHz Offset -131 -142 -153 -160 -165 -165 dBc/Hz CLK1 = 491

39、.52 MHz, OUT = 245.76 MHz Divide Ratio = 2 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 KHz Offset 100 kHz Offset 1 MHz Offset -125 -132 -140 -151 -157 -158 dBc/Hz See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND A

40、ND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12656 REV PAGE 9 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 2/ Limits Unit Min Typ Max CLOCK OUTPUT PHASE NOISE- Continued. CLK1 to LVPECL and additive phase noise Continued. CLK1 = 24

41、5.76 MHz, OUT = 61.44 MHz Divide Ratio = 4 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 KHz Offset 100 kHz Offset 1 MHz Offset -138 -144 -154 -163 -164 -165 dBC/Hz CLK1 to LVDS additive phase noise CLK1 = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = 1 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 KHz Offs

42、et 100 kHz Offset 1 MHz Offset 10 MHz Offset -100 -110 -118 -129 -135 -140 -148 dBC/Hz CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 KHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset -112 -122 -132 -142 -148 -152 -155 dBC/Hz CLK1 = 491.52 MHz, OUT

43、 = 245.76 MHz Divide Ratio = 2 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 KHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset -108 -118 -128 -138 -145 -148 -154 dBC/Hz See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA

44、 LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12656 REV PAGE 10 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 2/ Limits Unit Min Typ Max CLOCK OUTPUT PHASE NOISE- Continued. CLK1 to LVDS additive phase noise Continued. CLK1 =

45、491.52 MHz, OUT = 122.88 MHz Divide Ratio = 4 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 KHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset -118 -129 -136 -147 -153 -156 -158 dBC/Hz CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 KHz Offset 100 kHz O

46、ffset 1 MHz Offset 10 MHz Offset -108 -118 -128 -138 -145 -148 -155 dBC/Hz CLK1 = 245.76 MHz, OUT = 122.88 MHz Divide Ratio = 2 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 KHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset -118 -127 -137 -147 -154 -156 -158 dBC/Hz See footnote at end of table. Prov

47、ided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12656 REV PAGE 11 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 2/ Limits Unit Min Typ Max CLOCK OUTPUT PHASE NOISE- Continued. CLK1 to CMOS additive phase noise CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 KHz