DLA DSCC-VID-V62 12667-2013 MICROCIRCUIT DIGITAL 16 BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Origina

2、l date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, 16 BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS, MONOLITHIC SILICON 13-02-07 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12667 REV PAGE 1 OF 12 AMSC N

3、/A 5962-V047-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12667 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 16

4、 bit dual supply bus transceiver with configurable voltage translation and 3-state outputs microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establish

5、es an administrative control number for identifying the item on the engineering documentation: V62/12667 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVC16T245-EP 16 bit dual supply

6、bus transceiver with configurable voltage translation and 3-state outputs 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 48 JEDEC MO-153 Plastic small outline package 1.2.3 Lead finishes. The lead finishes are as specifi

7、ed below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND

8、MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12667 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range: (VCCA, VCCB) . -0.5 V to 6.5 V Input voltage range (VI): 2/ I/O ports (A port) -0.5 V to 6.5 V I/O ports (B port) -0.5 V to 6.5 V Control inputs . -0.5 V to 6.5 V V

9、oltage range applied to any output in the high impedance or power off stated, (VO): 2/ A port -0.5 V to 6.5 V B port -0.5 V to 6.5 V Voltage range applied to any output in the high or low state, (VO): 2/ 3/ A port -0.5 V to VCCA+ 0.5 V B port -0.5 V to VCCB+ 0.5 V Input clamp current, (IIK) (VI 0) .

10、 -50 mA Output clamp current, (IOK) (VO 0) -50 mA Continuous output current, (IO) 50 mA Continuous current through each VCCA, VCCB, and GND 100 mA Maximum junction temperature,( TJ) . 150 C Storage temperature range . -65C to 150C 1.4 Thermal characteristics. Thermal metric 4/ Case outline X Units J

11、unction to ambient thermal resistance, JA5/ 59.9 C/W Junction to case (top) thermal resistance, JCtop6/ 13.9 Junction to board thermal resistance, JB7/ 27.1 Junction to top characterization parameter, JT8/ 0.5 Junction to board characterization parameter, JB9/ 26.8 Junction to case (bottom) thermal

12、resistance, JCbot10/ N/A 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” i

13、s not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2/ The input and output negative voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The output positive-voltage may be exceeded up to 6.5 V maximum i

14、f the output current rating is observed. 4/ For more information about traditional and new thermal metric, see manufacturer “the IC package Thermal Metric application report, SPRA953”. 5/ The junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-stand

15、ard, high-k-board, as specified in JESD51-7, in an environment described in JESD51-2a. 6/ The junction to case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI stan

16、dard G30-88. 7/ The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. 8/ The junction to top characterization parameter, JT, estimates the junction temperature of a device in a rea

17、l system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 9/ The junction to board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obt

18、aining JA, using a procedure described in JESD51-2a (sections 6 and 7). 10/ The junction to case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standar

19、d G30-88 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12667 REV PAGE 4 1.5 Recommended operating conditions. 11/ 12/ 13/ 14/ 15/ VCCIVCCOLimits Unit Min Max Supply voltag

20、e VCCA1.65 5.5 V VCCB1.65 5.5 High level input voltage, (VIH) Data inputs 16/ 1.65 V to 1.95 V VCCIx 0.65 2.3 V to 2.7 V 1.7 3 V to 3.6 V 2 4.5 V to 5.5 V VCCIx 0.7 Low level input voltage, (VIL) Data inputs 16/ 1.65 V to 1.95 V VCCIx 0.35 2.3 V to 2.7 V 0.7 3 V to 3.6 V 0.8 4.5 V to 5.5 V VCCIx 0.3

21、 High level input voltage, (VIH) Control inputs (referenced to VCCA) 17/ 1.65 V to 1.95 V VCCAx 0.65 2.3 V to 2.7 V 1.7 3 V to 3.6 V 2 4.5 V to 5.5 V VCCAx 0.7 Low level input voltage, (VIL) Control inputs (referenced to VCCA) 17/ 1.65 V to 1.95 V VCCAx 0.35 2.3 V to 2.7 V 0.7 3 V to 3.6 V 0.8 4.5 V

22、 to 5.5 V VCCAx 0.3 Input voltage, (VI) Control inputs 0 5.5 Input/output voltage, (VI/O) Active state 0 VCCO3-State 0 5.5 High level output current, (IOH) 1.65 V to 1.95 V -4 mA 2.3 V to 2.7 V -8 3 V to 3.6 V -24 4.5 V to 5.5 V -32 Low level output current, (IOL) 1.65 V to 1.95 V 4 2.3 V to 2.7 V 8

23、 3 V to 3.6 V 24 4.5 V to 5.5 V 32 Input transition rise or fall rate, (t/v) Data inputs 1.65 V to 1.95 V 20 ns/V 2.3 V to 2.7 V 20 3 V to 3.6 V 10 4.5 V to 5.5 V 5 Operating free air temperature, (TA) -55 125 C _ 11/ Use of this product beyond the manufacturers design rules or stated parameters is

24、done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 12/ VCCI is the VCCassociated with the input port. 13/ VCCO is the VCCassociated with the output port. 14/ All unused or driven (floating) data inputs (I/Os)

25、 of the device must held at logic HIGH or LOW (preferably VCCI or GND) to ensure proper device operation and minimize power. Refer to manufacturer data, Implications of Slow or Floating CMOS inputs, literature number SCBA004. 15/ All unused data inputs of the device must be held at VCCAor GND to ens

26、ure proper device operation. 16/ For VCCIvalues not specified in the data sheet, VIHmin = VCCIx 0.7 V, VILmax = VCCIx 0.3 V. 17/ For VCCAvalues not specified in the data sheet, VIHmin = VCCAx 0.7 V, VILmax = VCCAx 0.3 V Provided by IHSNot for ResaleNo reproduction or networking permitted without lic

27、ense from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12667 REV PAGE 5 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51-2 Integrated Circuits Thermal Test Method E

28、nvironment Conditions Natural Convection (Still Air) JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages JESD51-8 Integrated Circuits Thermal Test Method Environment Conditions Junction-to-board thermal resistance Theta-JB or RJB(Copies of these documents are av

29、ailable online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240S, Arlington, VA 22201-2107). AMERICAN NATIONAL STANDARDS INSTITUTE (ANSI) STANDARD ANSI SEMI STANDARD G30-88 null Test Method for Junction-to-Case Thermal Resistance Measurements

30、for Ceramic Packages (Applications for copies should be addressed to the American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be perman

31、ently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) I.5 Unit container. The unit container shall be marked with the manufacturers part number and with items

32、A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.5, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimens

33、ions are as specified herein. I.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. I.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Function table. The function table shall be as shown in figure 3. 3.5.4 Logic diagram (P

34、ositive Logic). The logic diagram (Positive Logic) shall be as shown in figure 4. 3.5.5 Load circuit and voltage waveforms. The load circuit and voltage waveforms shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND

35、 AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12667 REV PAGE 6 TABLE I. Electrical performance characteristics. 1/ Test Test conditions VCCAVCCBLimits Unit Min Max Electrical characteristics 2/ 3/ TA= -55C to 125C, over recommended input voltage range (unless otherwise noted)

36、VOHIOH= -100 A, VI = VIH1.65 V to 4.5 V 1.65 V to 4.5 V VCCO 0.1 V IOH= -4 mA, VI = VIH1.65 V 1.65 V 1.2 IOH= -8 mA, VI = VIH2.3 V 2.3 V 1.9 IOH= -24 mA, VI = VIH3 V 3 V 2.35 IOH= -32 mA, VI = VIH4.5 V 4.5 V 3.75 VOLIOL= 100 A, VI = VIL1.65 V to 4.5 V 1.65 V to 4.5 V 0.1 IOL= 4 mA, VI = VIL1.65 V 1.

37、65 V 0.45 IOL= 8 mA, VI = VIL2.3 V 2.3 V 0.3 IOL= 24 mA, VI = VIL3 V 3 V 0.65 IOL= 32 mA, VI = VIL4.5 V 4.5 V 0.65 II Control inputs VI= VCCAor GND 1.65 V to 5.5 V 1.65 V to 5.5 V 2 A IoffA or B port VIor VO= 0 to 5.5 V 0 V 0 V to 5.5 V 10 0 V to 5.5 V 0 V 10 IOZA or B port VO= VCCOor GND, OE= VIH1.

38、65 V to 5.5 V 1.65 V to 5.5 V 10 ICCAVI= VCCIor GND, IO= 0 1.65 V to 5.5 V 1.65 V to 5.5 V 20 A 5 V 0 V 20 0 V 5 V -2.5 ICCBVI= VCCIor GND, IO= 0 1.65 V to 5.5 V 1.65 V to 5.5 V 20 A 5 V 0 V -2.5 0 V 5 V 20 ICCA+ ICCBVI= VCCIor GND, IO= 0 1.65 V to 5.5 V 1.65 V to 5.5 V 30 A ICCAA port One A port at

39、 VCCA 0.6 V, DIR at VCCA, B port = open 3 V to 5.5 V 3 V to 5.5 V 50 A DIR DIR at VCCA 0.6 V, B port = open, A port at VCCAor GND 50 ICCBB port One B port at VCCB 0.6 V, DIR at GND, A port = open 3 V to 5.5 V 3 V to 5.5 V 50 A CIControl inputs VI= VCCAor GND 3.3 V 3.3 V 4 TYP pF CIOA or B port VO= V

40、CCA/Bor GND 3.3 V 3.3 V 8.5 TYP pF See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12667 REV PAGE 7 TABLE I. Electrical performance characteris

41、tics - Continued. 1/ Parameter Test conditions From (Input) To (Output) VCCB= 1.8 V 0.15 V VCCB= 2.5 V 0.2 V VCCB= 3.3 V 0.3 V VCCB= 5 V 0.5 V Unit Min Max Min Max Min Max Min Max Switching characteristics TA= -55C to 125C, VCCA= 1.8 V 0.15 V (unless otherwise noted) (See FIGURE 5). tPLHA B 1.7 25.9

42、 1.3 13.2 1 11.4 0.8 11.1 ns tPHLtPLHB A 0.9 27.8 0.8 27.8 0.7 27.4 0.7 27.4 tPHLtPHZOEA 1.6 33.6 1.5 33.4 1.5 33.3 1.4 33.2 tPLZtPHZOEB 2.4 36.2 1.9 17.1 1.7 16 1.3 14.3 tPLZtPZHOEA 0.4 28 0.4 27.8 0.4 27.7 0.4 27.7 tPZLtPZHOEB 1.8 36 1.6 22 1.2 16.6 0.9 14.8 tPZLSwitching characteristics Continued

43、 TA= -55C to 125C, VCCA= 2.5 V 0.2 V (unless otherwise noted) (See FIGURE 5). tPLHA B 1.6 25.4 1.2 13 0.8 10.2 0.6 8.8 ns tPHLtPLHB A 1.2 13.3 1 13.1 1 12.9 0.9 12.8 tPHLtPHZOEA 1.4 13 1.4 13 1.4 13 1.4 13 tPLZtPHZOEB 2.3 33.6 1.8 14 1.7 14.3 0.9 10.9 tPLZtPZHOEA 1 14.9 1 14.9 1 14.9 1 14.9 tPZLtPZH

44、OEB 1.7 32.2 1.6 16.9 1.2 13.4 1 10.9 tPZLSwitching characteristics - Continued TA= -55C to 125C, VCCA= 3.3 V 0.3 V (unless otherwise noted) (See FIGURE 5). tPLHA B 1.5 25.2 1.1 12.8 0.8 10.2 0.5 8.4 ns tPHLtPLHB A 0.9 11.2 0.8 10.2 0.7 10.1 0.6 10 tPHLtPHZOEA 1.6 12.2 1.6 12.2 1.6 12.2 1.6 12.2 tPL

45、ZtPHZOEB 2.1 33 1.7 14.3 1.5 12.8 0.8 10.3 tPLZtPZHOEA 0.8 11.8 0.8 12.1 0.8 12.1 0.8 12.1 tPZLtPZHOEB 1.6 31.7 1.4 16.4 1.1 12.9 0.9 10.4 tPZLSee footnote at the end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COL

46、UMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12667 REV PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ Parameter Test conditions 5/ From (Input) To (Output) VCC= 1.8 V 0.15 V VCC= 2.5 V 0.2 V VCC= 3.3 V 0.3 V VCC= 5 V 0.5 V Unit Min Max Min Max Min Max Min Max Switching

47、 characteristics TA= -55C to 125C, VCCA= 5 V 0.5 V (unless otherwise noted) (See FIGURE 5). tPLHA B 1.6 25.4 1 14.3 0.7 10 0.4 8.2 ns tPHLtPLHB A 0.7 11 0.4 8.8 0.3 8.5 0.3 8.3 tPHLtPHZOEA 0.3 9.4 0.3 9.4 0.3 9.4 0.3 9.4 tPLZtPHZOEB 2 32.7 1.6 13.7 1.4 12 0.7 9.7 tPLZtPZHOEA 0.7 10.4 0.7 10.4 0.7 10.4 0.7 10.4 tPZLtPZHOEB 1.6 31.6 1.3 19.3 1 12.6 0.9 10 tPZLTest Symbol Test conditions VCCA= VCCB= 1.8 V VCCA= VCCB= 2.5 V VCCA= VCCB= 3.3 V VCCA= VCCB= 5 V Unit TYP TYP TYP TYP Operating characteristics TA = 25C A-port input, B-port output CpdA4/ CL = 0, f = 10 MHz tr= tf= 1 ns 2 2 2 3