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本文(DLA DSCC-VID-V62 13602-2013 MICROCIRCUIT DIGITAL LINEAR 16 BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS MONOLITHIC SILICON.pdf)为本站会员(吴艺期)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA DSCC-VID-V62 13602-2013 MICROCIRCUIT DIGITAL LINEAR 16 BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS MONOLITHIC SILICON.pdf

1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Original

2、date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL LINEAR, 16 BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS, MONOLITHIC SILICON 13-02-04 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/13602 REV PAGE 1 OF 12 A

3、MSC N/A 5962-V046-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13602 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performan

4、ce microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering document

5、ation: V62/13602 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74AVCB164245-EP 16 bit dual supply bus transceiver with configurable voltage translation and 3-state outputs 1.2.2 Case ou

6、tline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 48 JEDEC MO-153 Plastic Small Outline Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator

7、 Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13602 REV PAGE 3 1.3 Absolut

8、e maximum ratings. 1/ Supply voltage range: VCCA-0.5 V to 4.6 V VCCB-0.5 V to 4.6 V Input voltage range, (VI) 2/ I/O ports (A port) . -0.5 V to 4.6 V I/O ports (B port) . -0.5 V to 4.6 V Control inputs -0.5 V to 4.6 V Voltage range applied to any output in the high-impedance or power-off state, (VO)

9、 2/ A port -0.5 V to 4.6 V A port -0.5 V to 4.6 V Voltage range applied to any output in the high or low state, (VO) 2/ 3/ A port -0.5 V to VCCA+ 0.5 V A port -0.5 V to VCCB+ 0.5 V Input clamp current, (IIK) (VI 0) -50 mA Output clamp current, (IOK) (VO 0) . -50 mA Continuous output current, (IO) .

10、50 mA Continuous current through VCCA, VCCB, or GND 100 mA Maximum junction temperature, (TJ) 150 C Storage temperature range -65C to 150C 1.4 Thermal characteristics. Thermal metric 4/ Case outline X Units Junction to ambient thermal resistance, JA5/ 59.9 C/W Junction to case (top) thermal resistan

11、ce, JCtop6/ 13.9 Junction to board thermal resistance, JB7/ 27.1 Junction to top characterization parameter, JT8/ 0.5 Junction to board characterization parameter, JB9/ 26.8 Junction to case (bottom) thermal resistance, JCbot10/ N/A 1/ Stresses beyond those listed under “absolute maximum ratings” ma

12、y cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect

13、 device reliability. 2/ The input and output negative voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The output positive voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed. 4/ For more information about traditional an

14、d new thermal metrics, see manufacturer data. 5/ The junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K-board, as specified in JESD51-7, in an environment described in JESD51-2a. 6/ The junction to case (top) thermal resistance is

15、obtained by simulating a cold plate test on the package top. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 7/ The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to cont

16、rol the PCB temperature, as described in JESD51-8. 8/ The junction to top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 9/ The ju

17、nction to board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 10/ The junction to case (bottom) thermal resistance is obtained by

18、 simulating a cold plate test on the exposed (power) pad. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS,

19、OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13602 REV PAGE 4 1.4 Recommended operating conditions. 11/ 12/ 13/ 14/ VCCIVCCOLimits Unit Min Max Supply voltage VCCA1.4 3.6 V VCCB1.4 3.6 High level input voltage, (VIH) Data inputs 1.4 V to 1.95 V VCCIx 0.65 1.95 V to 2.7 V 1.7 2.7 V to 3.6 V 2 Low lev

20、el input voltage, (VIL) Data inputs 1.4 V to 1.95 V VCCIx 0.35 1.95 V to 2.7 V 0.7 2.7 V to 3.6 V 0.8 High level input voltage, (VIH) Control inputs (referenced to VCCB) 1.4 V to 1.95 V VCCBx 0.65 1.95 V to 2.7 V 1.7 2.7 V to 3.6 V 2 Low level input voltage, (VIL) Control inputs (referenced to VCCB)

21、 1.4 V to 1.95 V VCCBx 0.35 1.95 V to 2.7 V 0.7 2.7 V to 3.6 V 0.8 Input voltage, (VI) 0 3.6Output voltage, (VO) Active state 0 VCCO3-State 3.6High level output current, (IOH) 1.4 V to 1.6 V -2 mA 1.65 V to 1.95 V -4 2.3 V to 2.7 V -8 3 V to 3.6 V -12 Low level output current, (IOL) 1.4 V to 1.6 V 2

22、 mA 1.65 V to 1.95 V 4 2.3 V to 2.7 V 8 3 V to 3.6 V 12 Input transition rise or fall rate,(t/v) 5 ns/V Operating free air temperature, (TA) -55 125 C _ 11/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor m

23、aintain no responsibility or liability for product used beyond the stated limits. 12/ VCCI is the VCCassociated with the input port. 13/ VCCO is the VCCassociated with the output port. 14/ All unused data inputs of the device must held at VCCIor GND to ensure proper device operation. Refer to manufa

24、cturer data, Implications of Slow or Floating CMOS inputs, literature number SCBA004. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13602 REV PAGE 5 2. APPLICABLE DOCUMENT

25、S JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51 Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device). JESD51-2a Integrated Circuits Thermal Test Method Environment Conditions Natural Con

26、vection (Still Air) JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages JESD51-8 Integrated Circuits Thermal Test Method Environment Conditions Junction-to-board (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Tec

27、hnology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2107). AMERICAN NATIONAL STANDARDS INSTITUTE (ANSI) STANDARD ANSI SEMI STANDARD G30-88 Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be addressed to th

28、e American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in

29、 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maxi

30、mum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The cas

31、e outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Function table. The function table shall be as shown in figure 3. 3.5.4 Logic diagram (Positive Logic). The logic diagram (Positive Logic) shall be as shown in

32、 figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13602 REV PAGE 6 TABLE I. Electrical performance characteristics. 1/ Test Test conditions VCCAVCCB-55C to 125C Uni

33、t Min Max Electrical characteristics 2/ 3/ Over recommended operating free air temperature range (unless otherwise noted) VOHIOH= -100 A, VI = VIH1.4 V to 3.6 V 1.4 V to 3.6 V VCCO 0.2 V IOH= -2 mA, VI = VIH1.4 V 1.4 V 1.05 IOH= -4 mA, VI = VIH1.65 V 1.65 V 1.2 IOH= -8 mA, VI = VIH2.3 V 2.3 V 1.7 IO

34、H= -12 mA, VI = VIH3 V 3 V 2.2 VOLIOH= 100 A, VI = VIL1.4 V to 3.6 V 1.4 V to 3.6 V 0.2 IOH= 2 mA, VI = VIL1.4 V 1.4 V 0.35 IOH= 4 mA, VI = VIL1.65 V 1.65 V 0.45 IOH= 8 mA, VI = VIL2.3 V 2.3 V 0.6 IOH= 12 mA, VI = VIL3 V 3 V 0.75 II Control inputs VI= VCCBor GND 1.4 V to 3.6 V 1.4 V to 3.6 V 2.5 A I

35、offA port VIor VO= 0 to 3.6 V 0 V 0 V to 3.6 V 10 B port 0 V to 3.6 V 0 V 10 IOZ4/ A or B port VO= VCCOor GND, VI= VCCIor GND OEnullnullnullnull= VIH3.6 V 3.6 V 12.5 B port OEnullnullnullnull= dont care 0 V 3.6 V 12.5 A port 3.6 V 0 V 12.5 ICCAVI= VCCIor GND, IO= 0 1.6 V 1.6 V 35 A 1.95 V 1.95 V 35

36、2.7 V 2.7 V 45 0 V 3.6 V -50 3.6 V 0 V 50 3.6 V 3.6 V 50 ICCBVI= VCCIor GND, IO= 0 1.6 V 1.6 V 35 A 1.95 V 1.95 V 35 2.7 V 2.7 V 45 0 V 3.6 V 50 3.6 V 0 V -50 3.6 V 3.6 V 50 CIControl inputs VI= 3.3 V or GND, TA= 25C 3.3 V 3.3 V 4 TYP pF CIOA or B ports VO= 3.3 V or GND, TA= 25C 3.3 V 3.3 V 5 TYP pF

37、 See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13602 REV PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Parameter Tes

38、t conditions From (Input) To (Output)VCCB= 1.5 V 0.1 V VCCB= 1.8 V 0.15 V VCCB= 2.5 V 0.2 V VCCB= 3.3 V 0.3 V Unit Min Max Min Max Min Max Min Max Switching characteristics TA= -55C to 125C, VCCA= 1.5 V 0.1 V (See FIGURE 5). tpdA B 1.7 12.7 1.9 12.3 1.8 11.5 1.7 11.8 ns B A 1.8 12.8 2.2 13.4 2.1 13.

39、6 2.1 13.3 tenOEnullnullnullnullA 2.5 14.8 2.4 13.9 2.1 12.4 1.9 11.9 B 2.1 15 2.9 15.8 3.2 16 3 15.8 tdisOEnullnullnullnullA 2.2 12.9 2.3 12.1 1.3 9.6 1.3 9 B 2.1 13.1 2.3 12.4 1.7 11.1 1.6 10.8 Switching characteristics - Continued TA= -55C to 125C, VCCA= 1.8 V 0.15 V (See FIGURE 5). tpdA B 1.7 12

40、.7 1.8 12 1.7 10.7 1.6 10.3 ns B A 1.4 11.5 1.8 12 1.8 11.8 1.8 11.5 tenOEnullnullnullnullA 2.6 14.5 2.5 13.5 2.2 12.1 1.9 11.9 B 1.8 13.6 2.6 13.7 2.6 13.6 2.6 13.4 tdisOEnullnullnullnullA 2.3 13 2.3 12.1 1.3 9.6 1.3 9 B 1.8 13 2.5 12.3 1.8 10.7 1.7 10.4 Switching characteristics - Continued TA= -5

41、5C to 125C, VCCA= 2.5 V 0.2 V (See FIGURE 5). tpdA B 1.6 12 1.8 11.6 1.5 10 1.4 9.4 ns B A 1.3 10.6 1.7 10.4 1.5 10 1.4 9.7 tenOEnullnullnullnullA 3.1 14.5 2.5 13.5 2.2 11.3 1.9 10.2 B 1.7 11.7 2.2 11.5 2.2 11.3 2.2 11.1 tdisOEnullnullnullnullA 2.4 13 3 12.1 1.4 9.6 1.2 9 B 1.2 11.8 1.9 11 1.4 9.6 1

42、.3 9.3 Switching characteristics - Continued TA= -55C to 125C, VCCA= 3.3 V 0.3 V (See FIGURE 5). tpdA B 1.5 11.9 1.7 11.4 1.5 9.7 1.4 9.1 ns B A 1.3 10.5 1.6 9.8 1.5 9.3 1.4 9.1 tenOEnullnullnullnullA 2.6 14.3 2.5 13.4 2.2 11.2 1.9 10.1 B 1.6 11.3 2 10.5 2 10.3 1.9 10.1 tdisOEnullnullnullnullA 2.3 1

43、3 3 12 1.3 9.5 1.2 9.5 B 1.3 12.9 2.1 11.5 1.6 9.8 1.5 9.5 See footnote at the end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13602 REV PAGE 8 TABLE I. Electr

44、ical performance characteristics - Continued. 1/ Test Symbol Test conditions TYP Unit Operating characteristics VCCAand VCCB = 3.3 V, TA = 25C Power dissipation capacitance per transceiver, A-port input, B-port output. Outputs enabled CpdA(VCCA) CL= 0, f = 10 MHz 14 pF Outputs disabled 7 Power dissi

45、pation capacitance per transceiver, B-port input, A-port output. Outputs enabled 20 Outputs disabled 7 Power dissipation capacitance per transceiver, A-port input, B-port output. Outputs enabled CpdB(VCCB) 20 Outputs disabled 7 Power dissipation capacitance per transceiver, B-port input, A-port outp

46、ut. Outputs enabled 14 Outputs disabled 7 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not nec

47、essarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ VCCOis the VCCassociated with the output port. 3/ VCCIis the VCCassociated with the input port. 4/ For I/O ports, the parameter IOZincludes the input leakage curren

48、t. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13602 REV PAGE 9 Case X Dimensions Symbol Millimeters Symbol Millimeters Min Max Min Max A 1.20 E 7.90 8.30 A1 0.05 0.15 E1 6.00 6.2

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