DLA DSCC-VID-V62 13603-2013 MICROCIRCUIT LINEAR 2 5 V TO 3 3 V HIGH PERFORMANCE CLOCK BUFFER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Orig

2、inal date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, LINEAR, 2.5 V TO 3.3 V HIGH PERFORMANCE CLOCK BUFFER, MONOLITHIC SILICON 13-01-11 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/13603 REV PAGE 1 OF 13 AMSC N/A 5962-V038-13 Provided by IHSNot for ResaleN

3、o reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13603 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a 2.5 V to 3.3 V high performance clock buffer microcircuit, with a

4、n operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/13603 - 01 X

5、 E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 CDCVF2310-EP 2.5 V to 3.3 V high performance clock buffer 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number o

6、f pins JEDEC PUB 95 Package style X 24 JEDEC MO-153 Plastic Small Outline Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold

7、flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13603 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range, (VDD) . -0.5 V to 4.6 V Input

8、 voltage range, (VI) . -0.5 V to VDD+ 0.5 V 2/ 3/ Output voltage range, (VO) -0.5 V to VDD+ 0.5 V 2/ 3/ Input clamp current, (IIK) (VIVDD) 50 mA Output clamp current, (IOK) (VOVDD) 50 mA Continuous total output current, (IO) (VO= 0 to VDD) . 50 mA Package thermal impedance, (JA) 91.7 C/W 4/ Storage

9、temperature range -65C to 150C 1.4 Recommended operating conditions. 5/ 6/ Supply voltage, (VDD) . 2.3 V to 2.5 V nominal . 3.3 V nominal to 3.6 V Maximum low level input voltage, (VIL) VDD= 3 V to 3.6 V . 0.8 V VDD= 2.3 V to 2.7 V 0.7 V Minimum high level input voltage, (VIH) VDD= 3 V to 3.6 V . 2

10、V VDD= 2.3 V to 2.7 V 1.7 V Input voltage, (VI) . 0 V to VDD High level output current, (IOH) VDD= 3 V to 3.6 V . 12 mA VDD= 2.3 V to 2.7 V 6 mA Low level output current, (IOL) VDD= 3 V to 3.6 V . 12 mA VDD= 2.3 V to 2.7 V 6 mA Operating junction temperature, (TJ): . -55C to +125C 1/ Stresses beyond

11、 those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum

12、 rated conditions for extended periods may affect device reliability. 2/ The input and output negative voltage ratings may be exceeded if the input and output clamp-current rating are observed. 3/ This value is limited to 4.6 V maximum. 4/ The package thermal impedance is calculated in accordance wi

13、th JESD 51. 5/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits./ 6/ Unused inputs must be high or low to prevent them from f

14、loating. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13603 REV PAGE 4 1.5 Thermal characteristics. Thermal metric 7/ Case outline X Units Junction to ambient thermal res

15、istance, JA8/ 91.7 C/W Junction to case (top) thermal resistance, JCtop9/ 31.2 Junction to board thermal resistance, JB10/ 46.4 Junction to top characterization parameter, JT11/ 1.5 Junction to board characterization parameter, JB12/ 45.8 Junction to case (bottom) thermal resistance, JCbot13/ N/A 2.

16、 APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51 Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device). JESD51-2a Integrated Circuits Thermal Test Method Environment Co

17、nditions Natural Convection (Still Air) JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages JESD51-8 Integrated Circuits Thermal Test Method Environment Conditions Junction-to-board (Copies of these documents are available online at http:/www.jedec.org or from J

18、EDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2107). AMERICAN NATIONAL STANDARDS INSTITUTE (ANSI) STANDARD ANSI SEMI STANDARD G30-88 null Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies

19、should be addressed to the American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org) _ 7/ For more information about traditional and new thermal metrics, see manufacturer data. 8/ T

20、he junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K-board, as specified in JESD51-7, in an environment described in JESD51-2a. 9/ The junction to case (top) thermal resistance is obtained by simulating a cold plate test on the pa

21、ckage top. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 10/ The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8

22、. 11/ The junction to top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 12/ The junction to board characterization parameter, JB,

23、 estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 13/ The junction to case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (p

24、ower) pad. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13

25、603 REV PAGE 5 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container s

26、hall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and

27、physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal function. The

28、terminal function shall be as shown in figure 3. 3.5.4 Function table. The function table shall be as shown in figure 4. 3.5.5 Functional block diagram. The functional block diagram shall be as shown in figure 5. 3.5.6 Test load circuit. The test load circuit shall be as shown in figure 6. 3.5.7 Vol

29、tage waveforms propagation delay times. The voltage waveforms propagation delay times shall be as shown in figure 7. 3.5.8 Output skew. The output skew shall be as shown in figure 8. 3.5.9 Pulse skew. The pulse skew shall be as shown in figure 9. 3.5.10 Supply current vs Frequency. The supply curren

30、t vs Frequency shall be as shown in figure 10. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13603 REV PAGE 6 TABLE I. Electrical performance characteristics. 1/ Test Symb

31、ol Test conditions Limits Unit Min Typ 2/ Max Over recommended operating free air temperature range (unless otherwise noted) Input voltage VIKVDD= 3 V, II= -18 mA -1.2 V Input current IIVI = 0 V to VDD5 A Static device current IDD3/ CLK = 0 to VDD, IO= 0 mA 100 A Input capacitance CIVDD= 2.3 V to 3.

32、6 V, VI= 0 V or VDD2.5 pF Output capacitance COVDD= 2.3 V to 3.6 V, VI= 0 V or VDD2.8 VDD= 3.3 V 0.3 V High level output voltage VOHVDD= min to max, IOH= -100 A VDD 0.2 V VDD= 3 V, IOH= -12 mA 2.1 VDD= 3 V, IOH= -6 mA 2.4 Low level output voltage VOLVDD= min to max, IOL= 100 A 0.2 VDD= 3 V, IOL= 12

33、mA 0.8 VDD= 3 V, IOL= 6 mA 0.55 High level output current IOHVDD= 3 V, VO= 1 V -28 mA VDD= 3.3 V, VO= 1.65 V -36 VDD= 3.6 V, VO= 3.135 V -14 High level output current IOHVDD= 3 V, VO= 1.95 V 28 mA VDD= 3.3 V, VO= 1.65 V 36 VDD= 3.6 V, VO= 0.4 V 14 VDD= 2.5 V 0.2 V High level output voltage VOHVDD= m

34、in to max, IOH= -100 A VDD 0.2 V VDD= 3 V, IOH= -6 mA 1.8 Low level output voltage VOLVDD= min to max, IOL= 100 A 0.2 VDD= 3 V, IOL= 6 mA 0.55 High level output current IOHVDD= 2.3 V, VO= 1 V -15 mA VDD= 2.5 V, VO= 1.25 V -25 VDD= 2.7 V, VO= 2.375 V -10 High level output current IOHVDD= 2.3 V, VO= 1

35、.2 V 15 mA VDD= 2.5 V, VO= 1.25 V 25 VDD= 2.7 V, VO= 0.3 V 10 Timing requirements Over recommended ranges of supply voltage and operating free air temperature Clock frequency fclkVDD= 3 V to 3.6 V 0 200 MHz VDD= 2.3 V to 2.7 V 0 170 Jitter characteristics Characterized using this device performance

36、EVM when VDD= 3.3 V. Outputs not under test are terminated to 50 Additive phase jitter from input to output 1 YD tjitter12 kHz to 5 MHz, fout = 30.72 MHz 52 fs ms 12 kHz to 20 MHz, fout = 125 MHz 45 See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted wi

37、thout license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13603 REV PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions Limits Unit Min Typ Max Switching characteristics Over recommended operating free air t

38、emperature range (unless otherwise noted). VDD= 3.3 V 0.3 V (See FIGURE 6) CLK to Yn tPLHf = 0 MHz to 200 MHz For circuit load, see FIGURE 6 1.3 3.3 ns tPHLOutput skew (Ym to Yn) 4/ tsk(0)See FIGURE 8 100 ps Pulse skew tsk(p)See FIGURE 9 570 Part to part skew tsk(pp)500 Rise time trVO= 0.4 V to 2 V,

39、 See FIGURE 7 0.7 2 V/ns Fall time tfVO= 2 V to 0.4 V, See FIGURE 7 0.7 2 Enable setup time, G_high before CLK tsu(en)0.1 ns Disable setup time, G_low before CLK tsu(dis)0.1 Enable hold time, G_high after CLK th(en)0.4 Disable hold time, G_low after CLK th(dis)0.4 VDD= 2.5 V 0.2 V (See FIGURE 6) CLK

40、 to Yn tPLHf = 0 MHz to 200 MHz For circuit load, see FIGURE 6 1.5 4 ns tPHLOutput skew (Ym to Yn) 4/ tsk(0)See FIGURE 8 170 ps Pulse skew tsk(p)See FIGURE 9 680 Part to part skew tsk(pp)600 Rise time trVO= 0.4 V to 1.7 V, See FIGURE 7 0.5 1.4 V/ns Fall time tfVO= 1.7 V to 0.4 V, See FIGURE 7 0.5 1.

41、4 Enable setup time, G_high before CLK tsu(en)0.1 ns Disable setup time, G_low before CLK tsu(dis)0.1 Enable hold time, G_high after CLK th(en)0.4 Disable hold time, G_low after CLK th(dis)0.4 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product p

42、erformance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ All typical v

43、alues are at respective nominal VDD. 3/ For ICCover frequency, see FIGURE 10. 4/ The tsk(o) specification is only valid for equal loading of all outputs. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE

44、 IDENT NO. 16236 DWG NO. V62/13603 REV PAGE 8 Case X Dimensions Symbol Millimeters Symbol Millimeters Min Max Min Max A 1.20 E 4.30 4.50 A1 0.05 0.15 E1 6.20 6.60 b 0.19 0.30 e 0.65 BSC c 0.15 NOM L 0.50 0.75 D 7.70 7.90 NOTES: 1. All linear dimensions are in millimeters. Dimensioning and tolerancin

45、g per ASME Y14.5M-1994. 2. This drawing is subject to change without notice. 3. Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 each side. 4. Body width does not include interlead flash. Interlead flash shall not excee

46、d 0.25 each side. 5. Falls within JEDEC MO-153. FIGURE 1. Case outline. SEATINGPLANESEEDETAIL AbD1213E E1A1e0.10c0-8LDETAIL AGAGEPLANEM0.10124A0.25Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT

47、NO. 16236 DWG NO. V62/13603 REV PAGE 9 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 GND 24 CLK 2 VDD23 VDD3 1Y0 22 VDD4 1Y1 21 2Y0 5 1Y2 20 2Y1 6 GND 19 GND 7 GND 18 GND 8 1Y3 17 2Y2 9 1Y4 16 2Y3 10 VDD15 VDD11 1G 14 VDD12 2Y4 13 2G FIGURE 2. Terminal connections. Terminal number Terminal name I/O Description 11 1G I Output enable control for 1Y0:4 outputs. This output enable is active-high, meaning the