DLA DSCC-VID-V62 13604-2013 MICROCIRCUIT LINEAR 2 2 V TO 4 V 14 A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Origina

2、l date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, LINEAR, 2.2 V TO 4 V, 14 A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETS, MONOLITHIC SILICON 13-02-04 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/13604 REV PAGE 1 OF 12 AMSC N/A 5962-V044-13 P

3、rovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13604 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 2.2 V to 4 V, 14 A

4、output synchronous buck PWM switcher with integrated FETs microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control numb

5、er for identifying the item on the engineering documentation: V62/13604 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TPS54010-EP 2.2 V to 4 V, 14 A output synchronous buck PWM switcher w

6、ith integrated FETs 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 28 JEDEC MO-153 Plastic Small Outline Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the devic

7、e manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG

8、NO. V62/13604 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Input voltage range, (VI): SS/ENA, SYNC -0.3 V to 7 V RT -0.3 V to 6 V VSENSE . -0.3 V to 4 V PVIN, VIN . -0.3 V to 4.5 V BOOT . -0.3 V to 10 V Output voltage range, (VO): VBIAS, COMP, PWRGD -0.3 V to 7 V PH -0.6 to 6 V Source current, (VO):

9、PH internally limited, COMP, VBIAS 6 mA Sink current, (IS): PH 25 A COMP 6 mA SS/ENA, PWRGD 10 mA Voltage differential , AGND to PGND 0. 3 V Junction temperature range, (TJ): -55C to +150C Storage temperature range, (Tstg) . -65C to 150C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 3

10、00C Electrostatic Discharge (ESD) ratings: Human body model (HBM) . 1.5 kV CDM . 750 V 1.4 Recommended operating conditions. 2/ Input voltage, (VIN) 3 V to 4 V Power input voltage, (PVIN) . 2.2 V to 4 V Operating junction temperature . -55C to +125C 1/ Stresses beyond those listed under “absolute ma

11、ximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended p

12、eriods may affect device reliability. 2/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo re

13、production or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13604 REV PAGE 4 1.5 Thermal characteristics. Thermal metric 3/ Case outline X Units Junction to ambient thermal resistance, JA4/ 30.5 C/W Junction to case (to

14、p) thermal resistance, JCtop5/ 13.5 Junction to board thermal resistance, JB6/ 11.6 Junction to top characterization parameter, JT7/ 0.4 Junction to board characterization parameter, JB8/ 11.4 Junction to case (bottom) thermal resistance, JCbot9/ 0.9 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOL

15、OGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51 Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device). JESD51-2a Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) JESD51-

16、7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages JESD51-8 Integrated Circuits Thermal Test Method Environment Conditions Junction-to-board (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 N

17、orth 10th Street, Suite 240S, Arlington, VA 22201-2107). AMERICAN NATIONAL STANDARDS INSTITUTE (ANSI) STANDARD ANSI SEMI STANDARD G30-88 null Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be addressed to the American National St

18、andards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org) _ 3/ For more information about traditional and new thermal metrics, see manufacturer data. 4/ The junction to ambient thermal resistance under

19、 natural convection is obtained in a simulation on a JEDEC-standard, high-K-board, as specified in JESD51-7, in an environment described in JESD51-2a. 5/ The junction to case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specified JEDEC- standard test ex

20、ists, but a close description can be found in the ANSI SEMI standard G30-88. 6/ The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. 7/ The junction to top characterization parame

21、ter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 8/ The junction to board characterization parameter, JB, estimates the junction temperature of a device in

22、 a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 9/ The junction to case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specified JEDEC- standard test exists

23、, but a close description can be found in the ANSI SEMI standard G30-88 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13604 REV PAGE 5 3. REQUIREMENTS 3.1 Marking. Parts s

24、hall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number a

25、nd with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and p

26、hysical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal function shall be as shown in figure 3. 3.

27、5.4 Functional block diagram. The functional block diagram shall be as shown in figure 4. 3.5.5 Application circuit, 2.5 V to 1.5 V. The application circuit, 2.5 V to 1.5 V shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-

28、,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13604 REV PAGE 6 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test conditions 2/ Limits Unit Min Typ Max Supply voltage, VIN Input voltage VI3 4 V Supply voltage range PVIN Output = 1.8 V 2.2 4 Quiescen

29、t current VIN IQfs = 350 kHz, RT open, PH pin open, PVIN = 3.5 V, SYNC = 0 V 6.3 10 mA fs = 550 kHz, RT open, PH pin open, PVIN = 3.5 V, SYNC 2.5 V 8.3 13 Shutdown, SS/EA = 0 V, PVIN = 2.5 V 1 1.4 PVIN fs = 350 kHz, RT open, PH pin open, PVIN = 3.3 V, SYNC = 0 V 6 8 mA fs = 550 kHz, RT open, PH pin

30、open, PVIN = 3.5 V, SYNC 2.5 V, VIN = 3.3 V 6 10 Shutdown, SS/EA = 0 V, VIN = 3.3 V 90% Vref, otherwise PWRGD is low. Note that output is low when SS/ENA is low or the internal shutdown signal is active. RT 28 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching

31、frequency, fs. SS/ENA 26 Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and capacitor input to externally set the start-up time. SYNC 27 Synchronization input. data function pin which provides logic input to synchronize to an external

32、oscillator or pin select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be connected to the RT pin. VBIAS 25 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high q

33、uality, low-ESR 0.1 F to 1.0 F ceramic capacitor. VIN 24 Input supply for the internal control circuits. Bypass the VIN pin to the PGND pins close to device package with a high quality, low ESR 1 F ceramic capacitor. VSENSE 2 Error amplifier inverting input. Connect to output voltage compensation ne

34、twork/output divider. FIGURE 3. Terminal function. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13604 REV PAGE 10 FIGURE 4. Functional block diagram. FALLINGEDGED GLITCHT

35、HERMALSHUTDOWN150CFALLINGANDRISINGEDGED GLITCH1.2 VHYSTERESIS:0.03 VENABLECOMPARATOR2.5 s2.95 VHYSTERESIS:0.11 VVIN UVLOCOMPARATOR2.5 sVININTERNAL/EXTERNALSLOW-STARTINTERNAL SLOW-START TIME=3.35 ms+-VINREFERENCEVREF-0.891 VSHUTDOWNOSCLEADINGEDGEBLANKINGR QSADAPTIVE DEAD-TIMEANDCONTROL LOGICPWMCOMPAR

36、ATORSHUTDOWNREGVBIASAGND VBIASVINPVINOCOVBOOTPHOUTL3.0-4.0 V2.2-4.0 VVINFALLINGEDGED GLITCHPGNDPWRGD0.90 VrefHYSTERESIS:0.03 VrefPOWER-GOODCOMPARATOR35 sVSENSESHUTDOWNERRORAMPLIFIERSS/ENAVSENSE COMPSS_DIS8 m8 m100 nsILIMCOMPARATORRT SYNCProvided by IHSNot for ResaleNo reproduction or networking perm

37、itted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13604 REV PAGE 11 FIGURE 5. Application circuit, 2.5 V to 1.5 V. 2423222126 201425 13124 11103 98726518171 161519C30.047 F0.68 HL1C133300 pFR82.4C2100 FC120.1 F2728AGNDVSNSCOMPPWRGDVBIASSS

38、/ENASYNCRT VINPVINPVINPVINPVINPHPHPHPHPHPHPHPHPHBOOTPGNDPGNDPGNDPGNDPGNDPwPd1 2VOUTR471.5 k1.0 FC40.047 FC5C61200 pFR313.7 k33 pFC7C8820 pFR52.21 kR110.0 kR214.7 k1.0 FC1110 FC1010 FC9330 FC1PVINVINR610.0 kProvided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-

39、,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13604 REV PAGE 12 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures sho

40、uld include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard comme

41、rcial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data bo

42、ok. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availabili

43、ty as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http:/www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Transport media Vendor part number V62/13

44、604-01XE 01295 Tape and real TPS54010MPWPREP Tube TPS54010MPWPEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-