DLA DSCC-VID-V62 13606-2013 MICROCIRCUIT MEMORY 3 3 V CMOS FIRST-IN FIRST-OUT MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITI

2、ME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, MEMORY, 3.3 V CMOS FIRST-IN, FIRST-OUT, MONOLITHIC SILICON 13-06-20 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/13606 REV PAGE 1

3、 OF 36 AMSC N/A 5962-V042-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13606 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high p

4、erformance 3.3 V CMOS first-in, first-out (FIFO) microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for id

5、entifying the item on the engineering documentation: V62/13606 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device Memory organization Generic number Circuit function 01 4096 x 18 SN74V245-EP 3.3 V CMOS first-in first-out 1.2.

6、2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 64 MS-026 Plastic quad flat pack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator M

7、aterial A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range, (VCC) -0.5 V to + 5 V Continuous output current, (IO) (VO= 0 to VCC) 50 mA Maximum junction temperature (TJ) . 150C Storage temperature range, (TST

8、G) . -65C to +150C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not i

9、mplied. Exposure to absolute-maximum-rated conditions for extended periods may Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13606 REV PAGE 3 1.4 Recommended operating con

10、ditions. 2/ 3/ Supply voltage, (VCC) +3 V to +3.6 V High level input voltage, (VIH) +2.0 V to 5.0 V Low level input voltage, (VIL) . +0.8 V maximum Operating free air temperature, (TA) -55C to +125C 1.5 Thermal characteristics. Thermal metric Symbol Case X Unit Thermal resistance, junction-to-ambien

11、t 4/ JA46.1 C/W Thermal resistance, junction-to-case (top) 5/ JC(TOP)5.8 C/W Thermal resistance, junction-to-board 6/ JB19.7 C/W Characterization parameter, junction-to-top 7/ JT0.2 C/W Characterization parameter, junction-to-board 8/ JB19.4 C/W 2/ All unused inputs of the device must be held at VCC

12、or GND to ensure proper device operation. 3/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 4/ The thermal resistance, jun

13、ction-to-ambient under natural convection is obtained in a simulation on a JEDEC standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. 5/ The thermal resistance, junction-to-case (top) is obtained by simulating a cold plate test on the package top. No specific J

14、EDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 6/ The thermal resistance, junction-to-board is obtained by simulating in an environment with a ring cold plate fixture to control the printed circuit board (PCB) temperature, as described in JESD51-8.

15、7/ Characterization parameter, junction-to-top (JT) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 8/ Characterization parameter, junction-to-board (JB) estimates

16、 the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLU

17、MBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13606 REV PAGE 4 2. APPLICABLE DOCUMENTS AMERICAN NATIONAL STANDARDS INSTITUTE ANSI SEMI STANDARD G30-88 - Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be addressed to the Amer

18、ican National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org) JEDEC Solid State Technology Association JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices EIA/JESD51-2

19、a - Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) EIA/JESD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages EIA/JESD 51-8 - Integrated Circuits Thermal Test Method Environment Conditions Junction-to-Board (Applica

20、tions for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as fo

21、llows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended o

22、perating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as

23、 shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Truth table. The truth table shall be as shown in figure 3. 3.5.4 Logic diagram. The logic diagram shall be as shown in figure 4. 3.5.5 Test load circuit. The test load circuit sha

24、ll be as shown in figure 5. 3.5.6 Timing waveforms. The timing waveforms shall be as shown in figure 6. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13606 REV PAGE 5 TABL

25、E I. Electrical performance characteristics. 1/ Test Symbol ConditionsTemperature, TADevice type Limits Unit Min Max High level output voltage VOHVCC= 3 V, IOH= -2 mA -55C to +125C 01 2.4 V Low level output voltage VOLVCC= 3 V, IOL= 8 mA -55C to +125C 01 0.4 V Input current IIVCC= 3.6 V, VI= VCCto 0

26、.4 V -55C to +125C 01 1 A High impedance output current IOZVCC = 3.6 V, OE VIH, VO= VCCto 0.4 V -55C to +125C 01 10 A Supply current ICC1VCC= 3.3 V 2/ 3/ 4/ +25C 01 35 mA ICC2VCC= 3.6 V 2/ 5/ 5 mA Input capacitance CINVI= 0, f = 1 MHz +25C 01 10 typical pF Output capacitance COUTVO= 0, f = 1 MHz, ou

27、tput deselected, OE VIH+25C 01 10 typical pF Clock cycle frequency fclock-55C to +125C 01 66.7 MHz Data access time tA-55C to +125C 01 1 11 ns Clock cycle time tCLK-55C to +125C 01 16 ns Clock high time tCLKH-55C to +125C 01 7 ns Clock low time tCLKL-55C to +125C 01 7 ns Data setup time tDS-55C to +

28、125C 01 5 ns Data hold time tDH-55C to +125C 01 2 ns Enable setup time tENS-55C to +125C 01 5 ns Enable hold time tENH-55C to +125C 01 2 ns Load setup time tLDS-55C to +125C 01 5 ns Load hold time tLDH-55C to +125C 01 2 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction o

29、r networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13606 REV PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol ConditionsTemperature, TA Device type Limits Unit Min Max Reset pulse width 6/ t

30、RS-55C to +125C 01 16 ns Reset setup time tRSS-55C to +125C 01 10.5 ns Reset recovery time tRSR-55C to +125C 01 10.5 ns Reset to flag and output time tRSF-55C to +125C 01 16 ns Output enable to output in low Z tOLZ-55C to +125C 01 0 ns Output enable to output valid tOE-55C to +125C 01 1.5 9 ns Outpu

31、t enable to output in high Z tOHZ-55C to +125C 01 1.5 9 ns Write clock to full flag tWFF-55C to +125C 01 11 ns Read clock to empty flag tREF-55C to +125C 01 11 ns Clock to asynchronous programmable Almost Full flag tPAFA-55C to +125C 01 21 ns Write clock to synchronous programmable Almost Full flag

32、tPAFS-55C to +125C 01 11 ns Clock to asynchronous programmable Almost Empty flag tPAEA-55C to +125C 01 21 ns Read clock to synchronous programmable Almost Empty flag tPAES-55C to +125C 01 11 ns Clock to half full flag tHF-55C to +125C 01 21 ns Clock to expansion out tXO-55C to +125C 01 11 ns Expansi

33、on in pulse duration tXI-55C to +125C 01 7 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13606 REV PAGE 7 TABLE I. Electrical performance

34、 characteristics Continued. 1/ Test Symbol ConditionsTemperature, TA Device type Limits Unit Min Max Expansion in setup time tXIS-55C to +125C 01 6 ns Skew time between read clock and write clock for FF /IR and EF / OR tSKEW1-55C to +125C 01 6.5 ns Skew time between read clock and write clock for an

35、d PAE and PAF (synchronous only) tSKEW2-55C to +125C 01 18.5 ns 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all

36、parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Tested with outputs disabled (IOUT= 0). 3/ RCLK and WCLK switch at 20 MHz and data inputs switch at 10 MHz. 4/ Typical ICC1= 2.04 + 0.88 x fSW

37、+ 0.02 x CL x fSW(in mA). These equations are valid under the following conditions: VCC= 3.3 V, TA= +25C, fSW= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fSW/2, CL= capacitive load (in pF). 5/ All inputs = (VCC 0.2 V) or (GND +0.2 V), except RCLK and WCLK, which sw

38、itch at 20 MHz. 6/ Pulse durations less than minimum values are not allowed. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13606 REV PAGE 8 Case X FIGURE 1. Case outline.

39、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13606 REV PAGE 9 Case X Symbol Dimensions Inches Millimeters Min Max Min Max A - 0.047 - 1.20 A1 0.037 0.041 0.95 1.05 A2 0.0

40、09 - 0.25 - A3 0.001 - 0.05 - b 0.019 BSC 0.50 BSC c 0.005 NOM 0.13 NOM D/E 0.464 0.480 11.80 12.20 D1/E1 0.385 0.401 9.80 10.20 D2/E2 0.295 TYP 7.50 TYP L 0.017 0.029 0.45 0.75 NOTES: 1. Controlling dimensions are millimeter, inch dimensions are given for reference only. 2. Falls within reference t

41、o JEDEC MS-026. FIGURE 1. Case outline - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13606 REV PAGE 10 Device type 01 Case outline X Terminal number Terminal

42、symbol Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol 1 D15 17 PAE 33 VCC49 VCC2 D14 18 FL 34 Q4 50 Q15 3 D13 19 WCLK 35 GND 51 GND 4 D12 20 WEN 36 Q5 52 Q16 5 D11 21 WXI 37 Q6 53 Q17 6 D10 22 VCC38 Q7 54 EF / OR 7 D9 23 PAF 39 Q8 55 GND 8 D8 24 RXI 4

43、0 GND 56 VCC9 D7 25 FF /IR 41 Q9 57 RS 10 D6 26 WXO / HF 42 Q10 58 OE 11 D5 27 RXO 43 VCC59 LD 12 D4 28 Q0 44 Q11 60 REN 13 D3 29 Q1 45 Q12 61 RCLK 14 D2 30 GND 46 GND 62 GND 15 D1 31 Q2 47 Q13 63 D17 16 D0 32 Q3 48 Q14 64 D16 FIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduct

44、ion or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13606 REV PAGE 11 Terminal symbol I/O Description D0 D17 I Data inputs. Data inputs for an 18 bit bus. EF / OR O Memory empty/valid data available flag. In the standa

45、rd mode, the EF function is selected. EF indicates whether the FIFO memory is empty. In FWFT mode, the OR function is selected. OR indicates whether there is valid data available at the outputs. FF /IR O Memory full/space available flag. In the standard mode, the FF function is selected. FF indicate

46、s whether the FIFO memory is full. In the FWFT mode, the IR function is selected. IR indicates whether there is space available for writing to the FIFO memory. FL I Mode selection. In the single device or width expansion configuration, FL , together with WXI and RXI , determines if the mode or first

47、 word fall through (FWFT) mode, as well as whether the PAE / PAF flags are synchronous or asynchronous (see figure 3). In the daisy chain depth expansion configuration, FL is grounded on the first device (first load device) and set to high for all other devices in the daisy chain. GND Ground. LD I Read/write control. When LD is low, data on the inputs D0-D11 is written to the offset and depth registers on the low to high transition of the WCLK, when WEN is low. When LD is low, data on the outputs Q0-Q11 is read from the offset and depth registers on the low to high transiti